setup.c 33 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2004-2007 Cavium Networks
  7. * Copyright (C) 2008, 2009 Wind River Systems
  8. * written by Ralf Baechle <ralf@linux-mips.org>
  9. */
  10. #include <linux/compiler.h>
  11. #include <linux/vmalloc.h>
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/console.h>
  15. #include <linux/delay.h>
  16. #include <linux/export.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/memblock.h>
  20. #include <linux/serial.h>
  21. #include <linux/smp.h>
  22. #include <linux/types.h>
  23. #include <linux/string.h> /* for memset */
  24. #include <linux/tty.h>
  25. #include <linux/time.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/serial_core.h>
  28. #include <linux/serial_8250.h>
  29. #include <linux/of_fdt.h>
  30. #include <linux/libfdt.h>
  31. #include <linux/kexec.h>
  32. #include <asm/processor.h>
  33. #include <asm/reboot.h>
  34. #include <asm/smp-ops.h>
  35. #include <asm/irq_cpu.h>
  36. #include <asm/mipsregs.h>
  37. #include <asm/bootinfo.h>
  38. #include <asm/sections.h>
  39. #include <asm/fw/fw.h>
  40. #include <asm/setup.h>
  41. #include <asm/prom.h>
  42. #include <asm/time.h>
  43. #include <asm/octeon/octeon.h>
  44. #include <asm/octeon/pci-octeon.h>
  45. #include <asm/octeon/cvmx-rst-defs.h>
  46. /*
  47. * TRUE for devices having registers with little-endian byte
  48. * order, FALSE for registers with native-endian byte order.
  49. * PCI mandates little-endian, USB and SATA are configuraable,
  50. * but we chose little-endian for these.
  51. */
  52. const bool octeon_should_swizzle_table[256] = {
  53. [0x00] = true, /* bootbus/CF */
  54. [0x1b] = true, /* PCI mmio window */
  55. [0x1c] = true, /* PCI mmio window */
  56. [0x1d] = true, /* PCI mmio window */
  57. [0x1e] = true, /* PCI mmio window */
  58. [0x68] = true, /* OCTEON III USB */
  59. [0x69] = true, /* OCTEON III USB */
  60. [0x6c] = true, /* OCTEON III SATA */
  61. [0x6f] = true, /* OCTEON II USB */
  62. };
  63. EXPORT_SYMBOL(octeon_should_swizzle_table);
  64. #ifdef CONFIG_PCI
  65. extern void pci_console_init(const char *arg);
  66. #endif
  67. static unsigned long long max_memory = ULLONG_MAX;
  68. static unsigned long long reserve_low_mem;
  69. DEFINE_SEMAPHORE(octeon_bootbus_sem);
  70. EXPORT_SYMBOL(octeon_bootbus_sem);
  71. static struct octeon_boot_descriptor *octeon_boot_desc_ptr;
  72. struct cvmx_bootinfo *octeon_bootinfo;
  73. EXPORT_SYMBOL(octeon_bootinfo);
  74. #ifdef CONFIG_KEXEC
  75. #ifdef CONFIG_SMP
  76. /*
  77. * Wait for relocation code is prepared and send
  78. * secondary CPUs to spin until kernel is relocated.
  79. */
  80. static void octeon_kexec_smp_down(void *ignored)
  81. {
  82. int cpu = smp_processor_id();
  83. local_irq_disable();
  84. set_cpu_online(cpu, false);
  85. while (!atomic_read(&kexec_ready_to_reboot))
  86. cpu_relax();
  87. asm volatile (
  88. " sync \n"
  89. " synci ($0) \n");
  90. kexec_reboot();
  91. }
  92. #endif
  93. #define OCTEON_DDR0_BASE (0x0ULL)
  94. #define OCTEON_DDR0_SIZE (0x010000000ULL)
  95. #define OCTEON_DDR1_BASE (0x410000000ULL)
  96. #define OCTEON_DDR1_SIZE (0x010000000ULL)
  97. #define OCTEON_DDR2_BASE (0x020000000ULL)
  98. #define OCTEON_DDR2_SIZE (0x3e0000000ULL)
  99. #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL)
  100. static struct kimage *kimage_ptr;
  101. static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes)
  102. {
  103. int64_t addr;
  104. struct cvmx_bootmem_desc *bootmem_desc;
  105. bootmem_desc = cvmx_bootmem_get_desc();
  106. if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) {
  107. mem_size = OCTEON_MAX_PHY_MEM_SIZE;
  108. pr_err("Error: requested memory too large,"
  109. "truncating to maximum size\n");
  110. }
  111. bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
  112. bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
  113. addr = (OCTEON_DDR0_BASE + reserve_low_mem + low_reserved_bytes);
  114. bootmem_desc->head_addr = 0;
  115. if (mem_size <= OCTEON_DDR0_SIZE) {
  116. __cvmx_bootmem_phy_free(addr,
  117. mem_size - reserve_low_mem -
  118. low_reserved_bytes, 0);
  119. return;
  120. }
  121. __cvmx_bootmem_phy_free(addr,
  122. OCTEON_DDR0_SIZE - reserve_low_mem -
  123. low_reserved_bytes, 0);
  124. mem_size -= OCTEON_DDR0_SIZE;
  125. if (mem_size > OCTEON_DDR1_SIZE) {
  126. __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
  127. __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE,
  128. mem_size - OCTEON_DDR1_SIZE, 0);
  129. } else
  130. __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
  131. }
  132. static int octeon_kexec_prepare(struct kimage *image)
  133. {
  134. int i;
  135. char *bootloader = "kexec";
  136. octeon_boot_desc_ptr->argc = 0;
  137. for (i = 0; i < image->nr_segments; i++) {
  138. if (!strncmp(bootloader, (char *)image->segment[i].buf,
  139. strlen(bootloader))) {
  140. /*
  141. * convert command line string to array
  142. * of parameters (as bootloader does).
  143. */
  144. int argc = 0, offt;
  145. char *str = (char *)image->segment[i].buf;
  146. char *ptr = strchr(str, ' ');
  147. while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) {
  148. *ptr = '\0';
  149. if (ptr[1] != ' ') {
  150. offt = (int)(ptr - str + 1);
  151. octeon_boot_desc_ptr->argv[argc] =
  152. image->segment[i].mem + offt;
  153. argc++;
  154. }
  155. ptr = strchr(ptr + 1, ' ');
  156. }
  157. octeon_boot_desc_ptr->argc = argc;
  158. break;
  159. }
  160. }
  161. /*
  162. * Information about segments will be needed during pre-boot memory
  163. * initialization.
  164. */
  165. kimage_ptr = image;
  166. return 0;
  167. }
  168. static void octeon_generic_shutdown(void)
  169. {
  170. int i;
  171. #ifdef CONFIG_SMP
  172. int cpu;
  173. #endif
  174. struct cvmx_bootmem_desc *bootmem_desc;
  175. void *named_block_array_ptr;
  176. bootmem_desc = cvmx_bootmem_get_desc();
  177. named_block_array_ptr =
  178. cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr);
  179. #ifdef CONFIG_SMP
  180. /* disable watchdogs */
  181. for_each_online_cpu(cpu)
  182. cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
  183. #else
  184. cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
  185. #endif
  186. if (kimage_ptr != kexec_crash_image) {
  187. memset(named_block_array_ptr,
  188. 0x0,
  189. CVMX_BOOTMEM_NUM_NAMED_BLOCKS *
  190. sizeof(struct cvmx_bootmem_named_block_desc));
  191. /*
  192. * Mark all memory (except low 0x100000 bytes) as free.
  193. * It is the same thing that bootloader does.
  194. */
  195. kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL,
  196. 0x100000);
  197. /*
  198. * Allocate all segments to avoid their corruption during boot.
  199. */
  200. for (i = 0; i < kimage_ptr->nr_segments; i++)
  201. cvmx_bootmem_alloc_address(
  202. kimage_ptr->segment[i].memsz + 2*PAGE_SIZE,
  203. kimage_ptr->segment[i].mem - PAGE_SIZE,
  204. PAGE_SIZE);
  205. } else {
  206. /*
  207. * Do not mark all memory as free. Free only named sections
  208. * leaving the rest of memory unchanged.
  209. */
  210. struct cvmx_bootmem_named_block_desc *ptr =
  211. (struct cvmx_bootmem_named_block_desc *)
  212. named_block_array_ptr;
  213. for (i = 0; i < bootmem_desc->named_block_num_blocks; i++)
  214. if (ptr[i].size)
  215. cvmx_bootmem_free_named(ptr[i].name);
  216. }
  217. kexec_args[2] = 1UL; /* running on octeon_main_processor */
  218. kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
  219. #ifdef CONFIG_SMP
  220. secondary_kexec_args[2] = 0UL; /* running on secondary cpu */
  221. secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
  222. #endif
  223. }
  224. static void octeon_shutdown(void)
  225. {
  226. octeon_generic_shutdown();
  227. #ifdef CONFIG_SMP
  228. smp_call_function(octeon_kexec_smp_down, NULL, 0);
  229. smp_wmb();
  230. while (num_online_cpus() > 1) {
  231. cpu_relax();
  232. mdelay(1);
  233. }
  234. #endif
  235. }
  236. static void octeon_crash_shutdown(struct pt_regs *regs)
  237. {
  238. octeon_generic_shutdown();
  239. default_machine_crash_shutdown(regs);
  240. }
  241. #ifdef CONFIG_SMP
  242. void octeon_crash_smp_send_stop(void)
  243. {
  244. int cpu;
  245. /* disable watchdogs */
  246. for_each_online_cpu(cpu)
  247. cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
  248. }
  249. #endif
  250. #endif /* CONFIG_KEXEC */
  251. #ifdef CONFIG_CAVIUM_RESERVE32
  252. uint64_t octeon_reserve32_memory;
  253. EXPORT_SYMBOL(octeon_reserve32_memory);
  254. #endif
  255. #ifdef CONFIG_KEXEC
  256. /* crashkernel cmdline parameter is parsed _after_ memory setup
  257. * we also parse it here (workaround for EHB5200) */
  258. static uint64_t crashk_size, crashk_base;
  259. #endif
  260. static int octeon_uart;
  261. extern asmlinkage void handle_int(void);
  262. /**
  263. * Return non zero if we are currently running in the Octeon simulator
  264. *
  265. * Returns
  266. */
  267. int octeon_is_simulation(void)
  268. {
  269. return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
  270. }
  271. EXPORT_SYMBOL(octeon_is_simulation);
  272. /**
  273. * Return true if Octeon is in PCI Host mode. This means
  274. * Linux can control the PCI bus.
  275. *
  276. * Returns Non zero if Octeon in host mode.
  277. */
  278. int octeon_is_pci_host(void)
  279. {
  280. #ifdef CONFIG_PCI
  281. return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
  282. #else
  283. return 0;
  284. #endif
  285. }
  286. /**
  287. * Get the clock rate of Octeon
  288. *
  289. * Returns Clock rate in HZ
  290. */
  291. uint64_t octeon_get_clock_rate(void)
  292. {
  293. struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
  294. return sysinfo->cpu_clock_hz;
  295. }
  296. EXPORT_SYMBOL(octeon_get_clock_rate);
  297. static u64 octeon_io_clock_rate;
  298. u64 octeon_get_io_clock_rate(void)
  299. {
  300. return octeon_io_clock_rate;
  301. }
  302. EXPORT_SYMBOL(octeon_get_io_clock_rate);
  303. /**
  304. * Write to the LCD display connected to the bootbus. This display
  305. * exists on most Cavium evaluation boards. If it doesn't exist, then
  306. * this function doesn't do anything.
  307. *
  308. * @s: String to write
  309. */
  310. static void octeon_write_lcd(const char *s)
  311. {
  312. if (octeon_bootinfo->led_display_base_addr) {
  313. void __iomem *lcd_address =
  314. ioremap(octeon_bootinfo->led_display_base_addr,
  315. 8);
  316. int i;
  317. for (i = 0; i < 8; i++, s++) {
  318. if (*s)
  319. iowrite8(*s, lcd_address + i);
  320. else
  321. iowrite8(' ', lcd_address + i);
  322. }
  323. iounmap(lcd_address);
  324. }
  325. }
  326. /**
  327. * Return the console uart passed by the bootloader
  328. *
  329. * Returns uart (0 or 1)
  330. */
  331. static int octeon_get_boot_uart(void)
  332. {
  333. return (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
  334. 1 : 0;
  335. }
  336. /**
  337. * Get the coremask Linux was booted on.
  338. *
  339. * Returns Core mask
  340. */
  341. int octeon_get_boot_coremask(void)
  342. {
  343. return octeon_boot_desc_ptr->core_mask;
  344. }
  345. /**
  346. * Check the hardware BIST results for a CPU
  347. */
  348. void octeon_check_cpu_bist(void)
  349. {
  350. const int coreid = cvmx_get_core_num();
  351. unsigned long long mask;
  352. unsigned long long bist_val;
  353. /* Check BIST results for COP0 registers */
  354. mask = 0x1f00000000ull;
  355. bist_val = read_octeon_c0_icacheerr();
  356. if (bist_val & mask)
  357. pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
  358. coreid, bist_val);
  359. bist_val = read_octeon_c0_dcacheerr();
  360. if (bist_val & 1)
  361. pr_err("Core%d L1 Dcache parity error: "
  362. "CacheErr(dcache) = 0x%llx\n",
  363. coreid, bist_val);
  364. mask = 0xfc00000000000000ull;
  365. bist_val = read_c0_cvmmemctl();
  366. if (bist_val & mask)
  367. pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
  368. coreid, bist_val);
  369. write_octeon_c0_dcacheerr(0);
  370. }
  371. /**
  372. * Reboot Octeon
  373. *
  374. * @command: Command to pass to the bootloader. Currently ignored.
  375. */
  376. static void octeon_restart(char *command)
  377. {
  378. /* Disable all watchdogs before soft reset. They don't get cleared */
  379. #ifdef CONFIG_SMP
  380. int cpu;
  381. for_each_online_cpu(cpu)
  382. cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
  383. #else
  384. cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
  385. #endif
  386. mb();
  387. while (1)
  388. if (OCTEON_IS_OCTEON3())
  389. cvmx_write_csr(CVMX_RST_SOFT_RST, 1);
  390. else
  391. cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
  392. }
  393. /**
  394. * Permanently stop a core.
  395. *
  396. * @arg: Ignored.
  397. */
  398. static void octeon_kill_core(void *arg)
  399. {
  400. if (octeon_is_simulation())
  401. /* A break instruction causes the simulator stop a core */
  402. asm volatile ("break" ::: "memory");
  403. local_irq_disable();
  404. /* Disable watchdog on this core. */
  405. cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
  406. /* Spin in a low power mode. */
  407. while (true)
  408. asm volatile ("wait" ::: "memory");
  409. }
  410. /**
  411. * Halt the system
  412. */
  413. static void octeon_halt(void)
  414. {
  415. smp_call_function(octeon_kill_core, NULL, 0);
  416. switch (octeon_bootinfo->board_type) {
  417. case CVMX_BOARD_TYPE_NAO38:
  418. /* Driving a 1 to GPIO 12 shuts off this board */
  419. cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
  420. cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
  421. break;
  422. default:
  423. octeon_write_lcd("PowerOff");
  424. break;
  425. }
  426. octeon_kill_core(NULL);
  427. }
  428. static char __read_mostly octeon_system_type[80];
  429. static void __init init_octeon_system_type(void)
  430. {
  431. char const *board_type;
  432. board_type = cvmx_board_type_to_string(octeon_bootinfo->board_type);
  433. if (board_type == NULL) {
  434. struct device_node *root;
  435. int ret;
  436. root = of_find_node_by_path("/");
  437. ret = of_property_read_string(root, "model", &board_type);
  438. of_node_put(root);
  439. if (ret)
  440. board_type = "Unsupported Board";
  441. }
  442. snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)",
  443. board_type, octeon_model_get_string(read_c0_prid()));
  444. }
  445. /**
  446. * Return a string representing the system type
  447. *
  448. * Returns
  449. */
  450. const char *octeon_board_type_string(void)
  451. {
  452. return octeon_system_type;
  453. }
  454. const char *get_system_type(void)
  455. __attribute__ ((alias("octeon_board_type_string")));
  456. void octeon_user_io_init(void)
  457. {
  458. union octeon_cvmemctl cvmmemctl;
  459. /* Get the current settings for CP0_CVMMEMCTL_REG */
  460. cvmmemctl.u64 = read_c0_cvmmemctl();
  461. /* R/W If set, marked write-buffer entries time out the same
  462. * as as other entries; if clear, marked write-buffer entries
  463. * use the maximum timeout. */
  464. cvmmemctl.s.dismarkwblongto = 1;
  465. /* R/W If set, a merged store does not clear the write-buffer
  466. * entry timeout state. */
  467. cvmmemctl.s.dismrgclrwbto = 0;
  468. /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
  469. * word location for an IOBDMA. The other 8 bits come from the
  470. * SCRADDR field of the IOBDMA. */
  471. cvmmemctl.s.iobdmascrmsb = 0;
  472. /* R/W If set, SYNCWS and SYNCS only order marked stores; if
  473. * clear, SYNCWS and SYNCS only order unmarked
  474. * stores. SYNCWSMARKED has no effect when DISSYNCWS is
  475. * set. */
  476. cvmmemctl.s.syncwsmarked = 0;
  477. /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
  478. cvmmemctl.s.dissyncws = 0;
  479. /* R/W If set, no stall happens on write buffer full. */
  480. if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
  481. cvmmemctl.s.diswbfst = 1;
  482. else
  483. cvmmemctl.s.diswbfst = 0;
  484. /* R/W If set (and SX set), supervisor-level loads/stores can
  485. * use XKPHYS addresses with <48>==0 */
  486. cvmmemctl.s.xkmemenas = 0;
  487. /* R/W If set (and UX set), user-level loads/stores can use
  488. * XKPHYS addresses with VA<48>==0 */
  489. cvmmemctl.s.xkmemenau = 0;
  490. /* R/W If set (and SX set), supervisor-level loads/stores can
  491. * use XKPHYS addresses with VA<48>==1 */
  492. cvmmemctl.s.xkioenas = 0;
  493. /* R/W If set (and UX set), user-level loads/stores can use
  494. * XKPHYS addresses with VA<48>==1 */
  495. cvmmemctl.s.xkioenau = 0;
  496. /* R/W If set, all stores act as SYNCW (NOMERGE must be set
  497. * when this is set) RW, reset to 0. */
  498. cvmmemctl.s.allsyncw = 0;
  499. /* R/W If set, no stores merge, and all stores reach the
  500. * coherent bus in order. */
  501. cvmmemctl.s.nomerge = 0;
  502. /* R/W Selects the bit in the counter used for DID time-outs 0
  503. * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
  504. * between 1x and 2x this interval. For example, with
  505. * DIDTTO=3, expiration interval is between 16K and 32K. */
  506. cvmmemctl.s.didtto = 0;
  507. /* R/W If set, the (mem) CSR clock never turns off. */
  508. cvmmemctl.s.csrckalwys = 0;
  509. /* R/W If set, mclk never turns off. */
  510. cvmmemctl.s.mclkalwys = 0;
  511. /* R/W Selects the bit in the counter used for write buffer
  512. * flush time-outs (WBFLT+11) is the bit position in an
  513. * internal counter used to determine expiration. The write
  514. * buffer expires between 1x and 2x this interval. For
  515. * example, with WBFLT = 0, a write buffer expires between 2K
  516. * and 4K cycles after the write buffer entry is allocated. */
  517. cvmmemctl.s.wbfltime = 0;
  518. /* R/W If set, do not put Istream in the L2 cache. */
  519. cvmmemctl.s.istrnol2 = 0;
  520. /*
  521. * R/W The write buffer threshold. As per erratum Core-14752
  522. * for CN63XX, a sc/scd might fail if the write buffer is
  523. * full. Lowering WBTHRESH greatly lowers the chances of the
  524. * write buffer ever being full and triggering the erratum.
  525. */
  526. if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
  527. cvmmemctl.s.wbthresh = 4;
  528. else
  529. cvmmemctl.s.wbthresh = 10;
  530. /* R/W If set, CVMSEG is available for loads/stores in
  531. * kernel/debug mode. */
  532. #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
  533. cvmmemctl.s.cvmsegenak = 1;
  534. #else
  535. cvmmemctl.s.cvmsegenak = 0;
  536. #endif
  537. /* R/W If set, CVMSEG is available for loads/stores in
  538. * supervisor mode. */
  539. cvmmemctl.s.cvmsegenas = 0;
  540. /* R/W If set, CVMSEG is available for loads/stores in user
  541. * mode. */
  542. cvmmemctl.s.cvmsegenau = 0;
  543. write_c0_cvmmemctl(cvmmemctl.u64);
  544. /* Setup of CVMSEG is done in kernel-entry-init.h */
  545. if (smp_processor_id() == 0)
  546. pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
  547. CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
  548. CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
  549. if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
  550. union cvmx_iob_fau_timeout fau_timeout;
  551. /* Set a default for the hardware timeouts */
  552. fau_timeout.u64 = 0;
  553. fau_timeout.s.tout_val = 0xfff;
  554. /* Disable tagwait FAU timeout */
  555. fau_timeout.s.tout_enb = 0;
  556. cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
  557. }
  558. if ((!OCTEON_IS_MODEL(OCTEON_CN68XX) &&
  559. !OCTEON_IS_MODEL(OCTEON_CN7XXX)) ||
  560. OCTEON_IS_MODEL(OCTEON_CN70XX)) {
  561. union cvmx_pow_nw_tim nm_tim;
  562. nm_tim.u64 = 0;
  563. /* 4096 cycles */
  564. nm_tim.s.nw_tim = 3;
  565. cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
  566. }
  567. write_octeon_c0_icacheerr(0);
  568. write_c0_derraddr1(0);
  569. }
  570. /**
  571. * Early entry point for arch setup
  572. */
  573. void __init prom_init(void)
  574. {
  575. struct cvmx_sysinfo *sysinfo;
  576. const char *arg;
  577. char *p;
  578. int i;
  579. u64 t;
  580. int argc;
  581. #ifdef CONFIG_CAVIUM_RESERVE32
  582. int64_t addr = -1;
  583. #endif
  584. /*
  585. * The bootloader passes a pointer to the boot descriptor in
  586. * $a3, this is available as fw_arg3.
  587. */
  588. octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
  589. octeon_bootinfo =
  590. cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
  591. cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
  592. sysinfo = cvmx_sysinfo_get();
  593. memset(sysinfo, 0, sizeof(*sysinfo));
  594. sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
  595. sysinfo->phy_mem_desc_addr = (u64)phys_to_virt(octeon_bootinfo->phy_mem_desc_addr);
  596. if ((octeon_bootinfo->major_version > 1) ||
  597. (octeon_bootinfo->major_version == 1 &&
  598. octeon_bootinfo->minor_version >= 4))
  599. cvmx_coremask_copy(&sysinfo->core_mask,
  600. &octeon_bootinfo->ext_core_mask);
  601. else
  602. cvmx_coremask_set64(&sysinfo->core_mask,
  603. octeon_bootinfo->core_mask);
  604. /* Some broken u-boot pass garbage in upper bits, clear them out */
  605. if (!OCTEON_IS_MODEL(OCTEON_CN78XX))
  606. for (i = 512; i < 1024; i++)
  607. cvmx_coremask_clear_core(&sysinfo->core_mask, i);
  608. sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
  609. sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
  610. sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
  611. sysinfo->board_type = octeon_bootinfo->board_type;
  612. sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
  613. sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
  614. memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
  615. sizeof(sysinfo->mac_addr_base));
  616. sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
  617. memcpy(sysinfo->board_serial_number,
  618. octeon_bootinfo->board_serial_number,
  619. sizeof(sysinfo->board_serial_number));
  620. sysinfo->compact_flash_common_base_addr =
  621. octeon_bootinfo->compact_flash_common_base_addr;
  622. sysinfo->compact_flash_attribute_base_addr =
  623. octeon_bootinfo->compact_flash_attribute_base_addr;
  624. sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
  625. sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
  626. sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
  627. if (OCTEON_IS_OCTEON2()) {
  628. /* I/O clock runs at a different rate than the CPU. */
  629. union cvmx_mio_rst_boot rst_boot;
  630. rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
  631. octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
  632. } else if (OCTEON_IS_OCTEON3()) {
  633. /* I/O clock runs at a different rate than the CPU. */
  634. union cvmx_rst_boot rst_boot;
  635. rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
  636. octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
  637. } else {
  638. octeon_io_clock_rate = sysinfo->cpu_clock_hz;
  639. }
  640. t = read_c0_cvmctl();
  641. if ((t & (1ull << 27)) == 0) {
  642. /*
  643. * Setup the multiplier save/restore code if
  644. * CvmCtl[NOMUL] clear.
  645. */
  646. void *save;
  647. void *save_end;
  648. void *restore;
  649. void *restore_end;
  650. int save_len;
  651. int restore_len;
  652. int save_max = (char *)octeon_mult_save_end -
  653. (char *)octeon_mult_save;
  654. int restore_max = (char *)octeon_mult_restore_end -
  655. (char *)octeon_mult_restore;
  656. if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) {
  657. save = octeon_mult_save3;
  658. save_end = octeon_mult_save3_end;
  659. restore = octeon_mult_restore3;
  660. restore_end = octeon_mult_restore3_end;
  661. } else {
  662. save = octeon_mult_save2;
  663. save_end = octeon_mult_save2_end;
  664. restore = octeon_mult_restore2;
  665. restore_end = octeon_mult_restore2_end;
  666. }
  667. save_len = (char *)save_end - (char *)save;
  668. restore_len = (char *)restore_end - (char *)restore;
  669. if (!WARN_ON(save_len > save_max ||
  670. restore_len > restore_max)) {
  671. memcpy(octeon_mult_save, save, save_len);
  672. memcpy(octeon_mult_restore, restore, restore_len);
  673. }
  674. }
  675. /*
  676. * Only enable the LED controller if we're running on a CN38XX, CN58XX,
  677. * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
  678. */
  679. if (!octeon_is_simulation() &&
  680. octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
  681. cvmx_write_csr(CVMX_LED_EN, 0);
  682. cvmx_write_csr(CVMX_LED_PRT, 0);
  683. cvmx_write_csr(CVMX_LED_DBG, 0);
  684. cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
  685. cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
  686. cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
  687. cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
  688. cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
  689. cvmx_write_csr(CVMX_LED_EN, 1);
  690. }
  691. #ifdef CONFIG_CAVIUM_RESERVE32
  692. /*
  693. * We need to temporarily allocate all memory in the reserve32
  694. * region. This makes sure the kernel doesn't allocate this
  695. * memory when it is getting memory from the
  696. * bootloader. Later, after the memory allocations are
  697. * complete, the reserve32 will be freed.
  698. *
  699. * Allocate memory for RESERVED32 aligned on 2MB boundary. This
  700. * is in case we later use hugetlb entries with it.
  701. */
  702. addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
  703. 0, 0, 2 << 20,
  704. "CAVIUM_RESERVE32", 0);
  705. if (addr < 0)
  706. pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
  707. else
  708. octeon_reserve32_memory = addr;
  709. #endif
  710. #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
  711. if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
  712. pr_info("Skipping L2 locking due to reduced L2 cache size\n");
  713. } else {
  714. uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
  715. #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
  716. /* TLB refill */
  717. cvmx_l2c_lock_mem_region(ebase, 0x100);
  718. #endif
  719. #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
  720. /* General exception */
  721. cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
  722. #endif
  723. #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
  724. /* Interrupt handler */
  725. cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
  726. #endif
  727. #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
  728. cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
  729. cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
  730. #endif
  731. #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
  732. cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
  733. #endif
  734. }
  735. #endif
  736. octeon_check_cpu_bist();
  737. octeon_uart = octeon_get_boot_uart();
  738. #ifdef CONFIG_SMP
  739. octeon_write_lcd("LinuxSMP");
  740. #else
  741. octeon_write_lcd("Linux");
  742. #endif
  743. octeon_setup_delays();
  744. /*
  745. * BIST should always be enabled when doing a soft reset. L2
  746. * Cache locking for instance is not cleared unless BIST is
  747. * enabled. Unfortunately due to a chip errata G-200 for
  748. * Cn38XX and CN31XX, BIST must be disabled on these parts.
  749. */
  750. if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
  751. OCTEON_IS_MODEL(OCTEON_CN31XX))
  752. cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
  753. else
  754. cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
  755. /* Default to 64MB in the simulator to speed things up */
  756. if (octeon_is_simulation())
  757. max_memory = 64ull << 20;
  758. arg = strstr(arcs_cmdline, "mem=");
  759. if (arg) {
  760. max_memory = memparse(arg + 4, &p);
  761. if (max_memory == 0)
  762. max_memory = 32ull << 30;
  763. if (*p == '@')
  764. reserve_low_mem = memparse(p + 1, &p);
  765. }
  766. arcs_cmdline[0] = 0;
  767. argc = octeon_boot_desc_ptr->argc;
  768. for (i = 0; i < argc; i++) {
  769. const char *arg =
  770. cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
  771. if ((strncmp(arg, "MEM=", 4) == 0) ||
  772. (strncmp(arg, "mem=", 4) == 0)) {
  773. max_memory = memparse(arg + 4, &p);
  774. if (max_memory == 0)
  775. max_memory = 32ull << 30;
  776. if (*p == '@')
  777. reserve_low_mem = memparse(p + 1, &p);
  778. #ifdef CONFIG_KEXEC
  779. } else if (strncmp(arg, "crashkernel=", 12) == 0) {
  780. crashk_size = memparse(arg+12, &p);
  781. if (*p == '@')
  782. crashk_base = memparse(p+1, &p);
  783. strcat(arcs_cmdline, " ");
  784. strcat(arcs_cmdline, arg);
  785. /*
  786. * To do: switch parsing to new style, something like:
  787. * parse_crashkernel(arg, sysinfo->system_dram_size,
  788. * &crashk_size, &crashk_base);
  789. */
  790. #endif
  791. } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
  792. sizeof(arcs_cmdline) - 1) {
  793. strcat(arcs_cmdline, " ");
  794. strcat(arcs_cmdline, arg);
  795. }
  796. }
  797. if (strstr(arcs_cmdline, "console=") == NULL) {
  798. if (octeon_uart == 1)
  799. strcat(arcs_cmdline, " console=ttyS1,115200");
  800. else
  801. strcat(arcs_cmdline, " console=ttyS0,115200");
  802. }
  803. mips_hpt_frequency = octeon_get_clock_rate();
  804. octeon_init_cvmcount();
  805. _machine_restart = octeon_restart;
  806. _machine_halt = octeon_halt;
  807. #ifdef CONFIG_KEXEC
  808. _machine_kexec_shutdown = octeon_shutdown;
  809. _machine_crash_shutdown = octeon_crash_shutdown;
  810. _machine_kexec_prepare = octeon_kexec_prepare;
  811. #ifdef CONFIG_SMP
  812. _crash_smp_send_stop = octeon_crash_smp_send_stop;
  813. #endif
  814. #endif
  815. octeon_user_io_init();
  816. octeon_setup_smp();
  817. }
  818. /* Exclude a single page from the regions obtained in plat_mem_setup. */
  819. #ifndef CONFIG_CRASH_DUMP
  820. static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
  821. {
  822. if (addr > *mem && addr < *mem + *size) {
  823. u64 inc = addr - *mem;
  824. memblock_add(*mem, inc);
  825. *mem += inc;
  826. *size -= inc;
  827. }
  828. if (addr == *mem && *size > PAGE_SIZE) {
  829. *mem += PAGE_SIZE;
  830. *size -= PAGE_SIZE;
  831. }
  832. }
  833. #endif /* CONFIG_CRASH_DUMP */
  834. void __init fw_init_cmdline(void)
  835. {
  836. int i;
  837. octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
  838. for (i = 0; i < octeon_boot_desc_ptr->argc; i++) {
  839. const char *arg =
  840. cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
  841. if (strlen(arcs_cmdline) + strlen(arg) + 1 <
  842. sizeof(arcs_cmdline) - 1) {
  843. strcat(arcs_cmdline, " ");
  844. strcat(arcs_cmdline, arg);
  845. }
  846. }
  847. }
  848. void __init *plat_get_fdt(void)
  849. {
  850. octeon_bootinfo =
  851. cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
  852. return phys_to_virt(octeon_bootinfo->fdt_addr);
  853. }
  854. void __init plat_mem_setup(void)
  855. {
  856. uint64_t mem_alloc_size;
  857. uint64_t total;
  858. uint64_t crashk_end;
  859. #ifndef CONFIG_CRASH_DUMP
  860. int64_t memory;
  861. uint64_t kernel_start;
  862. uint64_t kernel_size;
  863. #endif
  864. total = 0;
  865. crashk_end = 0;
  866. /*
  867. * The Mips memory init uses the first memory location for
  868. * some memory vectors. When SPARSEMEM is in use, it doesn't
  869. * verify that the size is big enough for the final
  870. * vectors. Making the smallest chuck 4MB seems to be enough
  871. * to consistently work.
  872. */
  873. mem_alloc_size = 4 << 20;
  874. if (mem_alloc_size > max_memory)
  875. mem_alloc_size = max_memory;
  876. /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */
  877. #ifdef CONFIG_CRASH_DUMP
  878. memblock_add(reserve_low_mem, max_memory);
  879. total += max_memory;
  880. #else
  881. #ifdef CONFIG_KEXEC
  882. if (crashk_size > 0) {
  883. memblock_add(crashk_base, crashk_size);
  884. crashk_end = crashk_base + crashk_size;
  885. }
  886. #endif
  887. /*
  888. * When allocating memory, we want incrementing addresses,
  889. * which is handled by memblock
  890. */
  891. cvmx_bootmem_lock();
  892. while (total < max_memory) {
  893. memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
  894. __pa_symbol(&_end), -1,
  895. 0x100000,
  896. CVMX_BOOTMEM_FLAG_NO_LOCKING);
  897. if (memory >= 0) {
  898. u64 size = mem_alloc_size;
  899. #ifdef CONFIG_KEXEC
  900. uint64_t end;
  901. #endif
  902. /*
  903. * exclude a page at the beginning and end of
  904. * the 256MB PCIe 'hole' so the kernel will not
  905. * try to allocate multi-page buffers that
  906. * span the discontinuity.
  907. */
  908. memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
  909. &memory, &size);
  910. memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
  911. CVMX_PCIE_BAR1_PHYS_SIZE,
  912. &memory, &size);
  913. #ifdef CONFIG_KEXEC
  914. end = memory + mem_alloc_size;
  915. /*
  916. * This function automatically merges address regions
  917. * next to each other if they are received in
  918. * incrementing order
  919. */
  920. if (memory < crashk_base && end > crashk_end) {
  921. /* region is fully in */
  922. memblock_add(memory, crashk_base - memory);
  923. total += crashk_base - memory;
  924. memblock_add(crashk_end, end - crashk_end);
  925. total += end - crashk_end;
  926. continue;
  927. }
  928. if (memory >= crashk_base && end <= crashk_end)
  929. /*
  930. * Entire memory region is within the new
  931. * kernel's memory, ignore it.
  932. */
  933. continue;
  934. if (memory > crashk_base && memory < crashk_end &&
  935. end > crashk_end) {
  936. /*
  937. * Overlap with the beginning of the region,
  938. * reserve the beginning.
  939. */
  940. mem_alloc_size -= crashk_end - memory;
  941. memory = crashk_end;
  942. } else if (memory < crashk_base && end > crashk_base &&
  943. end < crashk_end)
  944. /*
  945. * Overlap with the beginning of the region,
  946. * chop of end.
  947. */
  948. mem_alloc_size -= end - crashk_base;
  949. #endif
  950. memblock_add(memory, mem_alloc_size);
  951. total += mem_alloc_size;
  952. /* Recovering mem_alloc_size */
  953. mem_alloc_size = 4 << 20;
  954. } else {
  955. break;
  956. }
  957. }
  958. cvmx_bootmem_unlock();
  959. /* Add the memory region for the kernel. */
  960. kernel_start = (unsigned long) _text;
  961. kernel_size = _end - _text;
  962. /* Adjust for physical offset. */
  963. kernel_start &= ~0xffffffff80000000ULL;
  964. memblock_add(kernel_start, kernel_size);
  965. #endif /* CONFIG_CRASH_DUMP */
  966. #ifdef CONFIG_CAVIUM_RESERVE32
  967. /*
  968. * Now that we've allocated the kernel memory it is safe to
  969. * free the reserved region. We free it here so that builtin
  970. * drivers can use the memory.
  971. */
  972. if (octeon_reserve32_memory)
  973. cvmx_bootmem_free_named("CAVIUM_RESERVE32");
  974. #endif /* CONFIG_CAVIUM_RESERVE32 */
  975. if (total == 0)
  976. panic("Unable to allocate memory from "
  977. "cvmx_bootmem_phy_alloc");
  978. }
  979. /*
  980. * Emit one character to the boot UART. Exported for use by the
  981. * watchdog timer.
  982. */
  983. void prom_putchar(char c)
  984. {
  985. uint64_t lsrval;
  986. /* Spin until there is room */
  987. do {
  988. lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
  989. } while ((lsrval & 0x20) == 0);
  990. /* Write the byte */
  991. cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
  992. }
  993. EXPORT_SYMBOL(prom_putchar);
  994. void __init prom_free_prom_memory(void)
  995. {
  996. if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
  997. /* Check for presence of Core-14449 fix. */
  998. u32 insn;
  999. u32 *foo;
  1000. foo = &insn;
  1001. asm volatile("# before" : : : "memory");
  1002. prefetch(foo);
  1003. asm volatile(
  1004. ".set push\n\t"
  1005. ".set noreorder\n\t"
  1006. "bal 1f\n\t"
  1007. "nop\n"
  1008. "1:\tlw %0,-12($31)\n\t"
  1009. ".set pop\n\t"
  1010. : "=r" (insn) : : "$31", "memory");
  1011. if ((insn >> 26) != 0x33)
  1012. panic("No PREF instruction at Core-14449 probe point.");
  1013. if (((insn >> 16) & 0x1f) != 28)
  1014. panic("OCTEON II DCache prefetch workaround not in place (%04x).\n"
  1015. "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).",
  1016. insn);
  1017. }
  1018. }
  1019. void __init octeon_fill_mac_addresses(void);
  1020. void __init device_tree_init(void)
  1021. {
  1022. const void *fdt;
  1023. bool do_prune;
  1024. bool fill_mac;
  1025. #ifdef CONFIG_MIPS_ELF_APPENDED_DTB
  1026. if (!fdt_check_header(&__appended_dtb)) {
  1027. fdt = &__appended_dtb;
  1028. do_prune = false;
  1029. fill_mac = true;
  1030. pr_info("Using appended Device Tree.\n");
  1031. } else
  1032. #endif
  1033. if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) {
  1034. fdt = phys_to_virt(octeon_bootinfo->fdt_addr);
  1035. if (fdt_check_header(fdt))
  1036. panic("Corrupt Device Tree passed to kernel.");
  1037. do_prune = false;
  1038. fill_mac = false;
  1039. pr_info("Using passed Device Tree.\n");
  1040. } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
  1041. fdt = &__dtb_octeon_68xx_begin;
  1042. do_prune = true;
  1043. fill_mac = true;
  1044. } else {
  1045. fdt = &__dtb_octeon_3xxx_begin;
  1046. do_prune = true;
  1047. fill_mac = true;
  1048. }
  1049. initial_boot_params = (void *)fdt;
  1050. if (do_prune) {
  1051. octeon_prune_device_tree();
  1052. pr_info("Using internal Device Tree.\n");
  1053. }
  1054. if (fill_mac)
  1055. octeon_fill_mac_addresses();
  1056. unflatten_and_copy_device_tree();
  1057. init_octeon_system_type();
  1058. }
  1059. static int __initdata disable_octeon_edac_p;
  1060. static int __init disable_octeon_edac(char *str)
  1061. {
  1062. disable_octeon_edac_p = 1;
  1063. return 0;
  1064. }
  1065. early_param("disable_octeon_edac", disable_octeon_edac);
  1066. static char *edac_device_names[] = {
  1067. "octeon_l2c_edac",
  1068. "octeon_pc_edac",
  1069. };
  1070. static int __init edac_devinit(void)
  1071. {
  1072. struct platform_device *dev;
  1073. int i, err = 0;
  1074. int num_lmc;
  1075. char *name;
  1076. if (disable_octeon_edac_p)
  1077. return 0;
  1078. for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) {
  1079. name = edac_device_names[i];
  1080. dev = platform_device_register_simple(name, -1, NULL, 0);
  1081. if (IS_ERR(dev)) {
  1082. pr_err("Registration of %s failed!\n", name);
  1083. err = PTR_ERR(dev);
  1084. }
  1085. }
  1086. num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 :
  1087. (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1);
  1088. for (i = 0; i < num_lmc; i++) {
  1089. dev = platform_device_register_simple("octeon_lmc_edac",
  1090. i, NULL, 0);
  1091. if (IS_ERR(dev)) {
  1092. pr_err("Registration of octeon_lmc_edac %d failed!\n", i);
  1093. err = PTR_ERR(dev);
  1094. }
  1095. }
  1096. return err;
  1097. }
  1098. device_initcall(edac_devinit);
  1099. static void __initdata *octeon_dummy_iospace;
  1100. static int __init octeon_no_pci_init(void)
  1101. {
  1102. /*
  1103. * Initially assume there is no PCI. The PCI/PCIe platform code will
  1104. * later re-initialize these to correct values if they are present.
  1105. */
  1106. octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT);
  1107. set_io_port_base((unsigned long)octeon_dummy_iospace);
  1108. ioport_resource.start = MAX_RESOURCE;
  1109. ioport_resource.end = 0;
  1110. return 0;
  1111. }
  1112. core_initcall(octeon_no_pci_init);
  1113. static int __init octeon_no_pci_release(void)
  1114. {
  1115. /*
  1116. * Release the allocated memory if a real IO space is there.
  1117. */
  1118. if ((unsigned long)octeon_dummy_iospace != mips_io_port_base)
  1119. vfree(octeon_dummy_iospace);
  1120. return 0;
  1121. }
  1122. late_initcall(octeon_no_pci_release);