cpu.c 8.4 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  7. * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/export.h>
  11. #include <linux/cpu.h>
  12. #include <asm/cpu.h>
  13. #include <asm/cpu-info.h>
  14. #include <asm/mipsregs.h>
  15. #include <bcm63xx_cpu.h>
  16. #include <bcm63xx_regs.h>
  17. #include <bcm63xx_io.h>
  18. #include <bcm63xx_irq.h>
  19. const unsigned long *bcm63xx_regs_base;
  20. EXPORT_SYMBOL(bcm63xx_regs_base);
  21. const int *bcm63xx_irqs;
  22. EXPORT_SYMBOL(bcm63xx_irqs);
  23. u16 bcm63xx_cpu_id __read_mostly;
  24. EXPORT_SYMBOL(bcm63xx_cpu_id);
  25. static u8 bcm63xx_cpu_rev;
  26. static unsigned int bcm63xx_cpu_freq;
  27. static unsigned int bcm63xx_memory_size;
  28. static const unsigned long bcm3368_regs_base[] = {
  29. __GEN_CPU_REGS_TABLE(3368)
  30. };
  31. static const int bcm3368_irqs[] = {
  32. __GEN_CPU_IRQ_TABLE(3368)
  33. };
  34. static const unsigned long bcm6328_regs_base[] = {
  35. __GEN_CPU_REGS_TABLE(6328)
  36. };
  37. static const int bcm6328_irqs[] = {
  38. __GEN_CPU_IRQ_TABLE(6328)
  39. };
  40. static const unsigned long bcm6338_regs_base[] = {
  41. __GEN_CPU_REGS_TABLE(6338)
  42. };
  43. static const int bcm6338_irqs[] = {
  44. __GEN_CPU_IRQ_TABLE(6338)
  45. };
  46. static const unsigned long bcm6345_regs_base[] = {
  47. __GEN_CPU_REGS_TABLE(6345)
  48. };
  49. static const int bcm6345_irqs[] = {
  50. __GEN_CPU_IRQ_TABLE(6345)
  51. };
  52. static const unsigned long bcm6348_regs_base[] = {
  53. __GEN_CPU_REGS_TABLE(6348)
  54. };
  55. static const int bcm6348_irqs[] = {
  56. __GEN_CPU_IRQ_TABLE(6348)
  57. };
  58. static const unsigned long bcm6358_regs_base[] = {
  59. __GEN_CPU_REGS_TABLE(6358)
  60. };
  61. static const int bcm6358_irqs[] = {
  62. __GEN_CPU_IRQ_TABLE(6358)
  63. };
  64. static const unsigned long bcm6362_regs_base[] = {
  65. __GEN_CPU_REGS_TABLE(6362)
  66. };
  67. static const int bcm6362_irqs[] = {
  68. __GEN_CPU_IRQ_TABLE(6362)
  69. };
  70. static const unsigned long bcm6368_regs_base[] = {
  71. __GEN_CPU_REGS_TABLE(6368)
  72. };
  73. static const int bcm6368_irqs[] = {
  74. __GEN_CPU_IRQ_TABLE(6368)
  75. };
  76. u8 bcm63xx_get_cpu_rev(void)
  77. {
  78. return bcm63xx_cpu_rev;
  79. }
  80. EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
  81. unsigned int bcm63xx_get_cpu_freq(void)
  82. {
  83. return bcm63xx_cpu_freq;
  84. }
  85. unsigned int bcm63xx_get_memory_size(void)
  86. {
  87. return bcm63xx_memory_size;
  88. }
  89. static unsigned int detect_cpu_clock(void)
  90. {
  91. u16 cpu_id = bcm63xx_get_cpu_id();
  92. switch (cpu_id) {
  93. case BCM3368_CPU_ID:
  94. return 300000000;
  95. case BCM6328_CPU_ID:
  96. {
  97. unsigned int tmp, mips_pll_fcvo;
  98. tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
  99. mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK)
  100. >> STRAPBUS_6328_FCVO_SHIFT;
  101. switch (mips_pll_fcvo) {
  102. case 0x12:
  103. case 0x14:
  104. case 0x19:
  105. return 160000000;
  106. case 0x1c:
  107. return 192000000;
  108. case 0x13:
  109. case 0x15:
  110. return 200000000;
  111. case 0x1a:
  112. return 384000000;
  113. case 0x16:
  114. return 400000000;
  115. default:
  116. return 320000000;
  117. }
  118. }
  119. case BCM6338_CPU_ID:
  120. /* BCM6338 has a fixed 240 Mhz frequency */
  121. return 240000000;
  122. case BCM6345_CPU_ID:
  123. /* BCM6345 has a fixed 140Mhz frequency */
  124. return 140000000;
  125. case BCM6348_CPU_ID:
  126. {
  127. unsigned int tmp, n1, n2, m1;
  128. /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
  129. tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
  130. n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
  131. n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
  132. m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
  133. n1 += 1;
  134. n2 += 2;
  135. m1 += 1;
  136. return (16 * 1000000 * n1 * n2) / m1;
  137. }
  138. case BCM6358_CPU_ID:
  139. {
  140. unsigned int tmp, n1, n2, m1;
  141. /* 16MHz * N1 * N2 / M1_CPU */
  142. tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
  143. n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
  144. n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
  145. m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
  146. return (16 * 1000000 * n1 * n2) / m1;
  147. }
  148. case BCM6362_CPU_ID:
  149. {
  150. unsigned int tmp, mips_pll_fcvo;
  151. tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
  152. mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK)
  153. >> STRAPBUS_6362_FCVO_SHIFT;
  154. switch (mips_pll_fcvo) {
  155. case 0x03:
  156. case 0x0b:
  157. case 0x13:
  158. case 0x1b:
  159. return 240000000;
  160. case 0x04:
  161. case 0x0c:
  162. case 0x14:
  163. case 0x1c:
  164. return 160000000;
  165. case 0x05:
  166. case 0x0e:
  167. case 0x16:
  168. case 0x1e:
  169. case 0x1f:
  170. return 400000000;
  171. case 0x06:
  172. return 440000000;
  173. case 0x07:
  174. case 0x17:
  175. return 384000000;
  176. case 0x15:
  177. case 0x1d:
  178. return 200000000;
  179. default:
  180. return 320000000;
  181. }
  182. }
  183. case BCM6368_CPU_ID:
  184. {
  185. unsigned int tmp, p1, p2, ndiv, m1;
  186. /* (64MHz / P1) * P2 * NDIV / M1_CPU */
  187. tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
  188. p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
  189. DMIPSPLLCFG_6368_P1_SHIFT;
  190. p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
  191. DMIPSPLLCFG_6368_P2_SHIFT;
  192. ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
  193. DMIPSPLLCFG_6368_NDIV_SHIFT;
  194. tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
  195. m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
  196. DMIPSPLLDIV_6368_MDIV_SHIFT;
  197. return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
  198. }
  199. default:
  200. panic("Failed to detect clock for CPU with id=%04X\n", cpu_id);
  201. }
  202. }
  203. /*
  204. * attempt to detect the amount of memory installed
  205. */
  206. static unsigned int detect_memory_size(void)
  207. {
  208. unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
  209. u32 val;
  210. if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
  211. return bcm_ddr_readl(DDR_CSEND_REG) << 24;
  212. if (BCMCPU_IS_6345()) {
  213. val = bcm_sdram_readl(SDRAM_MBASE_REG);
  214. return val * 8 * 1024 * 1024;
  215. }
  216. if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
  217. val = bcm_sdram_readl(SDRAM_CFG_REG);
  218. rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
  219. cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
  220. is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
  221. banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
  222. }
  223. if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
  224. val = bcm_memc_readl(MEMC_CFG_REG);
  225. rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
  226. cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
  227. is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
  228. banks = 2;
  229. }
  230. /* 0 => 11 address bits ... 2 => 13 address bits */
  231. rows += 11;
  232. /* 0 => 8 address bits ... 2 => 10 address bits */
  233. cols += 8;
  234. return 1 << (cols + rows + (is_32bits + 1) + banks);
  235. }
  236. void __init bcm63xx_cpu_init(void)
  237. {
  238. unsigned int tmp;
  239. unsigned int cpu = smp_processor_id();
  240. u32 chipid_reg;
  241. /* soc registers location depends on cpu type */
  242. chipid_reg = 0;
  243. switch (current_cpu_type()) {
  244. case CPU_BMIPS3300:
  245. if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT)
  246. __cpu_name[cpu] = "Broadcom BCM6338";
  247. fallthrough;
  248. case CPU_BMIPS32:
  249. chipid_reg = BCM_6345_PERF_BASE;
  250. break;
  251. case CPU_BMIPS4350:
  252. switch ((read_c0_prid() & PRID_REV_MASK)) {
  253. case 0x04:
  254. chipid_reg = BCM_3368_PERF_BASE;
  255. break;
  256. case 0x10:
  257. chipid_reg = BCM_6345_PERF_BASE;
  258. break;
  259. default:
  260. chipid_reg = BCM_6368_PERF_BASE;
  261. break;
  262. }
  263. break;
  264. }
  265. /*
  266. * really early to panic, but delaying panic would not help since we
  267. * will never get any working console
  268. */
  269. if (!chipid_reg)
  270. panic("unsupported Broadcom CPU");
  271. /* read out CPU type */
  272. tmp = bcm_readl(chipid_reg);
  273. bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
  274. bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
  275. switch (bcm63xx_cpu_id) {
  276. case BCM3368_CPU_ID:
  277. bcm63xx_regs_base = bcm3368_regs_base;
  278. bcm63xx_irqs = bcm3368_irqs;
  279. break;
  280. case BCM6328_CPU_ID:
  281. bcm63xx_regs_base = bcm6328_regs_base;
  282. bcm63xx_irqs = bcm6328_irqs;
  283. break;
  284. case BCM6338_CPU_ID:
  285. bcm63xx_regs_base = bcm6338_regs_base;
  286. bcm63xx_irqs = bcm6338_irqs;
  287. break;
  288. case BCM6345_CPU_ID:
  289. bcm63xx_regs_base = bcm6345_regs_base;
  290. bcm63xx_irqs = bcm6345_irqs;
  291. break;
  292. case BCM6348_CPU_ID:
  293. bcm63xx_regs_base = bcm6348_regs_base;
  294. bcm63xx_irqs = bcm6348_irqs;
  295. break;
  296. case BCM6358_CPU_ID:
  297. bcm63xx_regs_base = bcm6358_regs_base;
  298. bcm63xx_irqs = bcm6358_irqs;
  299. break;
  300. case BCM6362_CPU_ID:
  301. bcm63xx_regs_base = bcm6362_regs_base;
  302. bcm63xx_irqs = bcm6362_irqs;
  303. break;
  304. case BCM6368_CPU_ID:
  305. bcm63xx_regs_base = bcm6368_regs_base;
  306. bcm63xx_irqs = bcm6368_irqs;
  307. break;
  308. default:
  309. panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
  310. break;
  311. }
  312. bcm63xx_cpu_freq = detect_cpu_clock();
  313. bcm63xx_memory_size = detect_memory_size();
  314. pr_info("Detected Broadcom 0x%04x CPU revision %02x\n",
  315. bcm63xx_cpu_id, bcm63xx_cpu_rev);
  316. pr_info("CPU frequency is %u MHz\n",
  317. bcm63xx_cpu_freq / 1000000);
  318. pr_info("%uMB of RAM installed\n",
  319. bcm63xx_memory_size >> 20);
  320. }