clk.c 13 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  7. */
  8. #include <linux/init.h>
  9. #include <linux/export.h>
  10. #include <linux/mutex.h>
  11. #include <linux/err.h>
  12. #include <linux/clk.h>
  13. #include <linux/clkdev.h>
  14. #include <linux/delay.h>
  15. #include <bcm63xx_cpu.h>
  16. #include <bcm63xx_io.h>
  17. #include <bcm63xx_regs.h>
  18. #include <bcm63xx_reset.h>
  19. struct clk {
  20. void (*set)(struct clk *, int);
  21. unsigned int rate;
  22. unsigned int usage;
  23. int id;
  24. };
  25. static DEFINE_MUTEX(clocks_mutex);
  26. static void clk_enable_unlocked(struct clk *clk)
  27. {
  28. if (clk->set && (clk->usage++) == 0)
  29. clk->set(clk, 1);
  30. }
  31. static void clk_disable_unlocked(struct clk *clk)
  32. {
  33. if (clk->set && (--clk->usage) == 0)
  34. clk->set(clk, 0);
  35. }
  36. static void bcm_hwclock_set(u32 mask, int enable)
  37. {
  38. u32 reg;
  39. reg = bcm_perf_readl(PERF_CKCTL_REG);
  40. if (enable)
  41. reg |= mask;
  42. else
  43. reg &= ~mask;
  44. bcm_perf_writel(reg, PERF_CKCTL_REG);
  45. }
  46. /*
  47. * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
  48. */
  49. static void enet_misc_set(struct clk *clk, int enable)
  50. {
  51. u32 mask;
  52. if (BCMCPU_IS_6338())
  53. mask = CKCTL_6338_ENET_EN;
  54. else if (BCMCPU_IS_6345())
  55. mask = CKCTL_6345_ENET_EN;
  56. else if (BCMCPU_IS_6348())
  57. mask = CKCTL_6348_ENET_EN;
  58. else
  59. /* BCMCPU_IS_6358 */
  60. mask = CKCTL_6358_EMUSB_EN;
  61. bcm_hwclock_set(mask, enable);
  62. }
  63. static struct clk clk_enet_misc = {
  64. .set = enet_misc_set,
  65. };
  66. /*
  67. * Ethernet MAC clocks: only revelant on 6358, silently enable misc
  68. * clocks
  69. */
  70. static void enetx_set(struct clk *clk, int enable)
  71. {
  72. if (enable)
  73. clk_enable_unlocked(&clk_enet_misc);
  74. else
  75. clk_disable_unlocked(&clk_enet_misc);
  76. if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
  77. u32 mask;
  78. if (clk->id == 0)
  79. mask = CKCTL_6358_ENET0_EN;
  80. else
  81. mask = CKCTL_6358_ENET1_EN;
  82. bcm_hwclock_set(mask, enable);
  83. }
  84. }
  85. static struct clk clk_enet0 = {
  86. .id = 0,
  87. .set = enetx_set,
  88. };
  89. static struct clk clk_enet1 = {
  90. .id = 1,
  91. .set = enetx_set,
  92. };
  93. /*
  94. * Ethernet PHY clock
  95. */
  96. static void ephy_set(struct clk *clk, int enable)
  97. {
  98. if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
  99. bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
  100. }
  101. static struct clk clk_ephy = {
  102. .set = ephy_set,
  103. };
  104. /*
  105. * Ethernet switch SAR clock
  106. */
  107. static void swpkt_sar_set(struct clk *clk, int enable)
  108. {
  109. if (BCMCPU_IS_6368())
  110. bcm_hwclock_set(CKCTL_6368_SWPKT_SAR_EN, enable);
  111. else
  112. return;
  113. }
  114. static struct clk clk_swpkt_sar = {
  115. .set = swpkt_sar_set,
  116. };
  117. /*
  118. * Ethernet switch USB clock
  119. */
  120. static void swpkt_usb_set(struct clk *clk, int enable)
  121. {
  122. if (BCMCPU_IS_6368())
  123. bcm_hwclock_set(CKCTL_6368_SWPKT_USB_EN, enable);
  124. else
  125. return;
  126. }
  127. static struct clk clk_swpkt_usb = {
  128. .set = swpkt_usb_set,
  129. };
  130. /*
  131. * Ethernet switch clock
  132. */
  133. static void enetsw_set(struct clk *clk, int enable)
  134. {
  135. if (BCMCPU_IS_6328()) {
  136. bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable);
  137. } else if (BCMCPU_IS_6362()) {
  138. bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable);
  139. } else if (BCMCPU_IS_6368()) {
  140. if (enable) {
  141. clk_enable_unlocked(&clk_swpkt_sar);
  142. clk_enable_unlocked(&clk_swpkt_usb);
  143. } else {
  144. clk_disable_unlocked(&clk_swpkt_usb);
  145. clk_disable_unlocked(&clk_swpkt_sar);
  146. }
  147. bcm_hwclock_set(CKCTL_6368_ROBOSW_EN, enable);
  148. } else {
  149. return;
  150. }
  151. if (enable) {
  152. /* reset switch core afer clock change */
  153. bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
  154. msleep(10);
  155. bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);
  156. msleep(10);
  157. }
  158. }
  159. static struct clk clk_enetsw = {
  160. .set = enetsw_set,
  161. };
  162. /*
  163. * PCM clock
  164. */
  165. static void pcm_set(struct clk *clk, int enable)
  166. {
  167. if (BCMCPU_IS_3368())
  168. bcm_hwclock_set(CKCTL_3368_PCM_EN, enable);
  169. if (BCMCPU_IS_6358())
  170. bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
  171. }
  172. static struct clk clk_pcm = {
  173. .set = pcm_set,
  174. };
  175. /*
  176. * USB host clock
  177. */
  178. static void usbh_set(struct clk *clk, int enable)
  179. {
  180. if (BCMCPU_IS_6328())
  181. bcm_hwclock_set(CKCTL_6328_USBH_EN, enable);
  182. else if (BCMCPU_IS_6348())
  183. bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
  184. else if (BCMCPU_IS_6362())
  185. bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
  186. else if (BCMCPU_IS_6368())
  187. bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
  188. }
  189. static struct clk clk_usbh = {
  190. .set = usbh_set,
  191. };
  192. /*
  193. * USB device clock
  194. */
  195. static void usbd_set(struct clk *clk, int enable)
  196. {
  197. if (BCMCPU_IS_6328())
  198. bcm_hwclock_set(CKCTL_6328_USBD_EN, enable);
  199. else if (BCMCPU_IS_6362())
  200. bcm_hwclock_set(CKCTL_6362_USBD_EN, enable);
  201. else if (BCMCPU_IS_6368())
  202. bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
  203. }
  204. static struct clk clk_usbd = {
  205. .set = usbd_set,
  206. };
  207. /*
  208. * SPI clock
  209. */
  210. static void spi_set(struct clk *clk, int enable)
  211. {
  212. u32 mask;
  213. if (BCMCPU_IS_6338())
  214. mask = CKCTL_6338_SPI_EN;
  215. else if (BCMCPU_IS_6348())
  216. mask = CKCTL_6348_SPI_EN;
  217. else if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
  218. mask = CKCTL_6358_SPI_EN;
  219. else if (BCMCPU_IS_6362())
  220. mask = CKCTL_6362_SPI_EN;
  221. else
  222. /* BCMCPU_IS_6368 */
  223. mask = CKCTL_6368_SPI_EN;
  224. bcm_hwclock_set(mask, enable);
  225. }
  226. static struct clk clk_spi = {
  227. .set = spi_set,
  228. };
  229. /*
  230. * HSSPI clock
  231. */
  232. static void hsspi_set(struct clk *clk, int enable)
  233. {
  234. u32 mask;
  235. if (BCMCPU_IS_6328())
  236. mask = CKCTL_6328_HSSPI_EN;
  237. else if (BCMCPU_IS_6362())
  238. mask = CKCTL_6362_HSSPI_EN;
  239. else
  240. return;
  241. bcm_hwclock_set(mask, enable);
  242. }
  243. static struct clk clk_hsspi = {
  244. .set = hsspi_set,
  245. };
  246. /*
  247. * HSSPI PLL
  248. */
  249. static struct clk clk_hsspi_pll;
  250. /*
  251. * XTM clock
  252. */
  253. static void xtm_set(struct clk *clk, int enable)
  254. {
  255. if (!BCMCPU_IS_6368())
  256. return;
  257. if (enable)
  258. clk_enable_unlocked(&clk_swpkt_sar);
  259. else
  260. clk_disable_unlocked(&clk_swpkt_sar);
  261. bcm_hwclock_set(CKCTL_6368_SAR_EN, enable);
  262. if (enable) {
  263. /* reset sar core afer clock change */
  264. bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);
  265. mdelay(1);
  266. bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);
  267. mdelay(1);
  268. }
  269. }
  270. static struct clk clk_xtm = {
  271. .set = xtm_set,
  272. };
  273. /*
  274. * IPsec clock
  275. */
  276. static void ipsec_set(struct clk *clk, int enable)
  277. {
  278. if (BCMCPU_IS_6362())
  279. bcm_hwclock_set(CKCTL_6362_IPSEC_EN, enable);
  280. else if (BCMCPU_IS_6368())
  281. bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable);
  282. }
  283. static struct clk clk_ipsec = {
  284. .set = ipsec_set,
  285. };
  286. /*
  287. * PCIe clock
  288. */
  289. static void pcie_set(struct clk *clk, int enable)
  290. {
  291. if (BCMCPU_IS_6328())
  292. bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
  293. else if (BCMCPU_IS_6362())
  294. bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
  295. }
  296. static struct clk clk_pcie = {
  297. .set = pcie_set,
  298. };
  299. /*
  300. * Internal peripheral clock
  301. */
  302. static struct clk clk_periph = {
  303. .rate = (50 * 1000 * 1000),
  304. };
  305. /*
  306. * Linux clock API implementation
  307. */
  308. int clk_enable(struct clk *clk)
  309. {
  310. mutex_lock(&clocks_mutex);
  311. clk_enable_unlocked(clk);
  312. mutex_unlock(&clocks_mutex);
  313. return 0;
  314. }
  315. EXPORT_SYMBOL(clk_enable);
  316. void clk_disable(struct clk *clk)
  317. {
  318. if (!clk)
  319. return;
  320. mutex_lock(&clocks_mutex);
  321. clk_disable_unlocked(clk);
  322. mutex_unlock(&clocks_mutex);
  323. }
  324. EXPORT_SYMBOL(clk_disable);
  325. struct clk *clk_get_parent(struct clk *clk)
  326. {
  327. return NULL;
  328. }
  329. EXPORT_SYMBOL(clk_get_parent);
  330. int clk_set_parent(struct clk *clk, struct clk *parent)
  331. {
  332. return 0;
  333. }
  334. EXPORT_SYMBOL(clk_set_parent);
  335. unsigned long clk_get_rate(struct clk *clk)
  336. {
  337. if (!clk)
  338. return 0;
  339. return clk->rate;
  340. }
  341. EXPORT_SYMBOL(clk_get_rate);
  342. int clk_set_rate(struct clk *clk, unsigned long rate)
  343. {
  344. return 0;
  345. }
  346. EXPORT_SYMBOL_GPL(clk_set_rate);
  347. long clk_round_rate(struct clk *clk, unsigned long rate)
  348. {
  349. return 0;
  350. }
  351. EXPORT_SYMBOL_GPL(clk_round_rate);
  352. static struct clk_lookup bcm3368_clks[] = {
  353. /* fixed rate clocks */
  354. CLKDEV_INIT(NULL, "periph", &clk_periph),
  355. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  356. CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
  357. /* gated clocks */
  358. CLKDEV_INIT(NULL, "enet0", &clk_enet0),
  359. CLKDEV_INIT(NULL, "enet1", &clk_enet1),
  360. CLKDEV_INIT(NULL, "ephy", &clk_ephy),
  361. CLKDEV_INIT(NULL, "usbh", &clk_usbh),
  362. CLKDEV_INIT(NULL, "usbd", &clk_usbd),
  363. CLKDEV_INIT(NULL, "spi", &clk_spi),
  364. CLKDEV_INIT(NULL, "pcm", &clk_pcm),
  365. CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
  366. CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
  367. };
  368. static struct clk_lookup bcm6328_clks[] = {
  369. /* fixed rate clocks */
  370. CLKDEV_INIT(NULL, "periph", &clk_periph),
  371. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  372. CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
  373. CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
  374. /* gated clocks */
  375. CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
  376. CLKDEV_INIT(NULL, "usbh", &clk_usbh),
  377. CLKDEV_INIT(NULL, "usbd", &clk_usbd),
  378. CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
  379. CLKDEV_INIT(NULL, "pcie", &clk_pcie),
  380. };
  381. static struct clk_lookup bcm6338_clks[] = {
  382. /* fixed rate clocks */
  383. CLKDEV_INIT(NULL, "periph", &clk_periph),
  384. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  385. /* gated clocks */
  386. CLKDEV_INIT(NULL, "enet0", &clk_enet0),
  387. CLKDEV_INIT(NULL, "enet1", &clk_enet1),
  388. CLKDEV_INIT(NULL, "ephy", &clk_ephy),
  389. CLKDEV_INIT(NULL, "usbh", &clk_usbh),
  390. CLKDEV_INIT(NULL, "usbd", &clk_usbd),
  391. CLKDEV_INIT(NULL, "spi", &clk_spi),
  392. CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
  393. };
  394. static struct clk_lookup bcm6345_clks[] = {
  395. /* fixed rate clocks */
  396. CLKDEV_INIT(NULL, "periph", &clk_periph),
  397. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  398. /* gated clocks */
  399. CLKDEV_INIT(NULL, "enet0", &clk_enet0),
  400. CLKDEV_INIT(NULL, "enet1", &clk_enet1),
  401. CLKDEV_INIT(NULL, "ephy", &clk_ephy),
  402. CLKDEV_INIT(NULL, "usbh", &clk_usbh),
  403. CLKDEV_INIT(NULL, "usbd", &clk_usbd),
  404. CLKDEV_INIT(NULL, "spi", &clk_spi),
  405. CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
  406. };
  407. static struct clk_lookup bcm6348_clks[] = {
  408. /* fixed rate clocks */
  409. CLKDEV_INIT(NULL, "periph", &clk_periph),
  410. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  411. /* gated clocks */
  412. CLKDEV_INIT(NULL, "enet0", &clk_enet0),
  413. CLKDEV_INIT(NULL, "enet1", &clk_enet1),
  414. CLKDEV_INIT(NULL, "ephy", &clk_ephy),
  415. CLKDEV_INIT(NULL, "usbh", &clk_usbh),
  416. CLKDEV_INIT(NULL, "usbd", &clk_usbd),
  417. CLKDEV_INIT(NULL, "spi", &clk_spi),
  418. CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
  419. CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet_misc),
  420. };
  421. static struct clk_lookup bcm6358_clks[] = {
  422. /* fixed rate clocks */
  423. CLKDEV_INIT(NULL, "periph", &clk_periph),
  424. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  425. CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
  426. /* gated clocks */
  427. CLKDEV_INIT(NULL, "enet0", &clk_enet0),
  428. CLKDEV_INIT(NULL, "enet1", &clk_enet1),
  429. CLKDEV_INIT(NULL, "ephy", &clk_ephy),
  430. CLKDEV_INIT(NULL, "usbh", &clk_usbh),
  431. CLKDEV_INIT(NULL, "usbd", &clk_usbd),
  432. CLKDEV_INIT(NULL, "spi", &clk_spi),
  433. CLKDEV_INIT(NULL, "pcm", &clk_pcm),
  434. CLKDEV_INIT(NULL, "swpkt_sar", &clk_swpkt_sar),
  435. CLKDEV_INIT(NULL, "swpkt_usb", &clk_swpkt_usb),
  436. CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
  437. CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
  438. };
  439. static struct clk_lookup bcm6362_clks[] = {
  440. /* fixed rate clocks */
  441. CLKDEV_INIT(NULL, "periph", &clk_periph),
  442. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  443. CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
  444. CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
  445. /* gated clocks */
  446. CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
  447. CLKDEV_INIT(NULL, "usbh", &clk_usbh),
  448. CLKDEV_INIT(NULL, "usbd", &clk_usbd),
  449. CLKDEV_INIT(NULL, "spi", &clk_spi),
  450. CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
  451. CLKDEV_INIT(NULL, "pcie", &clk_pcie),
  452. CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
  453. };
  454. static struct clk_lookup bcm6368_clks[] = {
  455. /* fixed rate clocks */
  456. CLKDEV_INIT(NULL, "periph", &clk_periph),
  457. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  458. CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
  459. /* gated clocks */
  460. CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
  461. CLKDEV_INIT(NULL, "usbh", &clk_usbh),
  462. CLKDEV_INIT(NULL, "usbd", &clk_usbd),
  463. CLKDEV_INIT(NULL, "spi", &clk_spi),
  464. CLKDEV_INIT(NULL, "xtm", &clk_xtm),
  465. CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
  466. };
  467. #define HSSPI_PLL_HZ_6328 133333333
  468. #define HSSPI_PLL_HZ_6362 400000000
  469. static int __init bcm63xx_clk_init(void)
  470. {
  471. switch (bcm63xx_get_cpu_id()) {
  472. case BCM3368_CPU_ID:
  473. clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
  474. break;
  475. case BCM6328_CPU_ID:
  476. clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328;
  477. clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
  478. break;
  479. case BCM6338_CPU_ID:
  480. clkdev_add_table(bcm6338_clks, ARRAY_SIZE(bcm6338_clks));
  481. break;
  482. case BCM6345_CPU_ID:
  483. clkdev_add_table(bcm6345_clks, ARRAY_SIZE(bcm6345_clks));
  484. break;
  485. case BCM6348_CPU_ID:
  486. clkdev_add_table(bcm6348_clks, ARRAY_SIZE(bcm6348_clks));
  487. break;
  488. case BCM6358_CPU_ID:
  489. clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks));
  490. break;
  491. case BCM6362_CPU_ID:
  492. clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;
  493. clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks));
  494. break;
  495. case BCM6368_CPU_ID:
  496. clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks));
  497. break;
  498. }
  499. return 0;
  500. }
  501. arch_initcall(bcm63xx_clk_init);