ar5312.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391
  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
  7. * Copyright (C) 2006 FON Technology, SL.
  8. * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
  9. * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
  10. * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
  11. */
  12. /*
  13. * Platform devices for Atheros AR5312 SoCs
  14. */
  15. #include <linux/init.h>
  16. #include <linux/kernel.h>
  17. #include <linux/bitops.h>
  18. #include <linux/irqdomain.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/memblock.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/mtd/physmap.h>
  23. #include <linux/reboot.h>
  24. #include <asm/bootinfo.h>
  25. #include <asm/reboot.h>
  26. #include <asm/time.h>
  27. #include <ath25_platform.h>
  28. #include "devices.h"
  29. #include "ar5312.h"
  30. #include "ar5312_regs.h"
  31. static void __iomem *ar5312_rst_base;
  32. static struct irq_domain *ar5312_misc_irq_domain;
  33. static inline u32 ar5312_rst_reg_read(u32 reg)
  34. {
  35. return __raw_readl(ar5312_rst_base + reg);
  36. }
  37. static inline void ar5312_rst_reg_write(u32 reg, u32 val)
  38. {
  39. __raw_writel(val, ar5312_rst_base + reg);
  40. }
  41. static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
  42. {
  43. u32 ret = ar5312_rst_reg_read(reg);
  44. ret &= ~mask;
  45. ret |= val;
  46. ar5312_rst_reg_write(reg, ret);
  47. }
  48. static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
  49. {
  50. u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
  51. u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
  52. u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
  53. u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
  54. pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
  55. proc_addr, proc1, dma_addr, dma1);
  56. machine_restart("AHB error"); /* Catastrophic failure */
  57. return IRQ_HANDLED;
  58. }
  59. static void ar5312_misc_irq_handler(struct irq_desc *desc)
  60. {
  61. u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
  62. ar5312_rst_reg_read(AR5312_IMR);
  63. unsigned nr, misc_irq = 0;
  64. if (pending) {
  65. struct irq_domain *domain = irq_desc_get_handler_data(desc);
  66. nr = __ffs(pending);
  67. misc_irq = irq_find_mapping(domain, nr);
  68. }
  69. if (misc_irq) {
  70. generic_handle_irq(misc_irq);
  71. if (nr == AR5312_MISC_IRQ_TIMER)
  72. ar5312_rst_reg_read(AR5312_TIMER);
  73. } else {
  74. spurious_interrupt();
  75. }
  76. }
  77. /* Enable the specified AR5312_MISC_IRQ interrupt */
  78. static void ar5312_misc_irq_unmask(struct irq_data *d)
  79. {
  80. ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
  81. }
  82. /* Disable the specified AR5312_MISC_IRQ interrupt */
  83. static void ar5312_misc_irq_mask(struct irq_data *d)
  84. {
  85. ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
  86. ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
  87. }
  88. static struct irq_chip ar5312_misc_irq_chip = {
  89. .name = "ar5312-misc",
  90. .irq_unmask = ar5312_misc_irq_unmask,
  91. .irq_mask = ar5312_misc_irq_mask,
  92. };
  93. static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
  94. irq_hw_number_t hw)
  95. {
  96. irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
  97. return 0;
  98. }
  99. static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
  100. .map = ar5312_misc_irq_map,
  101. };
  102. static void ar5312_irq_dispatch(void)
  103. {
  104. u32 pending = read_c0_status() & read_c0_cause();
  105. if (pending & CAUSEF_IP2)
  106. do_IRQ(AR5312_IRQ_WLAN0);
  107. else if (pending & CAUSEF_IP5)
  108. do_IRQ(AR5312_IRQ_WLAN1);
  109. else if (pending & CAUSEF_IP6)
  110. do_IRQ(AR5312_IRQ_MISC);
  111. else if (pending & CAUSEF_IP7)
  112. do_IRQ(ATH25_IRQ_CPU_CLOCK);
  113. else
  114. spurious_interrupt();
  115. }
  116. void __init ar5312_arch_init_irq(void)
  117. {
  118. struct irq_domain *domain;
  119. unsigned irq;
  120. ath25_irq_dispatch = ar5312_irq_dispatch;
  121. domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
  122. &ar5312_misc_irq_domain_ops, NULL);
  123. if (!domain)
  124. panic("Failed to add IRQ domain");
  125. irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
  126. if (request_irq(irq, ar5312_ahb_err_handler, 0, "ar5312-ahb-error",
  127. NULL))
  128. pr_err("Failed to register ar5312-ahb-error interrupt\n");
  129. irq_set_chained_handler_and_data(AR5312_IRQ_MISC,
  130. ar5312_misc_irq_handler, domain);
  131. ar5312_misc_irq_domain = domain;
  132. }
  133. static struct physmap_flash_data ar5312_flash_data = {
  134. .width = 2,
  135. };
  136. static struct resource ar5312_flash_resource = {
  137. .start = AR5312_FLASH_BASE,
  138. .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
  139. .flags = IORESOURCE_MEM,
  140. };
  141. static struct platform_device ar5312_physmap_flash = {
  142. .name = "physmap-flash",
  143. .id = 0,
  144. .dev.platform_data = &ar5312_flash_data,
  145. .resource = &ar5312_flash_resource,
  146. .num_resources = 1,
  147. };
  148. static void __init ar5312_flash_init(void)
  149. {
  150. void __iomem *flashctl_base;
  151. u32 ctl;
  152. flashctl_base = ioremap(AR5312_FLASHCTL_BASE,
  153. AR5312_FLASHCTL_SIZE);
  154. ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
  155. ctl &= AR5312_FLASHCTL_MW;
  156. /* fixup flash width */
  157. switch (ctl) {
  158. case AR5312_FLASHCTL_MW16:
  159. ar5312_flash_data.width = 2;
  160. break;
  161. case AR5312_FLASHCTL_MW8:
  162. default:
  163. ar5312_flash_data.width = 1;
  164. break;
  165. }
  166. /*
  167. * Configure flash bank 0.
  168. * Assume 8M window size. Flash will be aliased if it's smaller
  169. */
  170. ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE;
  171. ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S;
  172. ctl |= 0x07 << AR5312_FLASHCTL_WST1_S;
  173. ctl |= 0x07 << AR5312_FLASHCTL_WST2_S;
  174. __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
  175. /* Disable other flash banks */
  176. ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
  177. ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
  178. __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
  179. ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
  180. ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
  181. __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
  182. iounmap(flashctl_base);
  183. }
  184. void __init ar5312_init_devices(void)
  185. {
  186. struct ath25_boarddata *config;
  187. ar5312_flash_init();
  188. /* Locate board/radio config data */
  189. ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
  190. config = ath25_board.config;
  191. /* AR2313 has CPU minor rev. 10 */
  192. if ((current_cpu_data.processor_id & 0xff) == 0x0a)
  193. ath25_soc = ATH25_SOC_AR2313;
  194. /* AR2312 shares the same Silicon ID as AR5312 */
  195. else if (config->flags & BD_ISCASPER)
  196. ath25_soc = ATH25_SOC_AR2312;
  197. /* Everything else is probably AR5312 or compatible */
  198. else
  199. ath25_soc = ATH25_SOC_AR5312;
  200. platform_device_register(&ar5312_physmap_flash);
  201. switch (ath25_soc) {
  202. case ATH25_SOC_AR5312:
  203. if (!ath25_board.radio)
  204. return;
  205. if (!(config->flags & BD_WLAN0))
  206. break;
  207. ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
  208. break;
  209. case ATH25_SOC_AR2312:
  210. case ATH25_SOC_AR2313:
  211. if (!ath25_board.radio)
  212. return;
  213. break;
  214. default:
  215. break;
  216. }
  217. if (config->flags & BD_WLAN1)
  218. ath25_add_wmac(1, AR5312_WLAN1_BASE, AR5312_IRQ_WLAN1);
  219. }
  220. static void ar5312_restart(char *command)
  221. {
  222. /* reset the system */
  223. local_irq_disable();
  224. while (1)
  225. ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
  226. }
  227. /*
  228. * This table is indexed by bits 5..4 of the CLOCKCTL1 register
  229. * to determine the predevisor value.
  230. */
  231. static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
  232. static unsigned __init ar5312_cpu_frequency(void)
  233. {
  234. u32 scratch, devid, clock_ctl1;
  235. u32 predivide_mask, multiplier_mask, doubler_mask;
  236. unsigned predivide_shift, multiplier_shift;
  237. unsigned predivide_select, predivisor, multiplier;
  238. /* Trust the bootrom's idea of cpu frequency. */
  239. scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
  240. if (scratch)
  241. return scratch;
  242. devid = ar5312_rst_reg_read(AR5312_REV);
  243. devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S;
  244. if (devid == AR5312_REV_MAJ_AR2313) {
  245. predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
  246. predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
  247. multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
  248. multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
  249. doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
  250. } else { /* AR5312 and AR2312 */
  251. predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
  252. predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
  253. multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
  254. multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
  255. doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
  256. }
  257. /*
  258. * Clocking is derived from a fixed 40MHz input clock.
  259. *
  260. * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
  261. * sys_freq = cpu_freq / 4 (used for APB clock, serial,
  262. * flash, Timer, Watchdog Timer)
  263. *
  264. * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
  265. *
  266. * So, for example, with a PLL multiplier of 5, we have
  267. *
  268. * cpu_freq = 200MHz
  269. * sys_freq = 50MHz
  270. * cnt_freq = 100MHz
  271. *
  272. * We compute the CPU frequency, based on PLL settings.
  273. */
  274. clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
  275. predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
  276. predivisor = clockctl1_predivide_table[predivide_select];
  277. multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
  278. if (clock_ctl1 & doubler_mask)
  279. multiplier <<= 1;
  280. return (40000000 / predivisor) * multiplier;
  281. }
  282. static inline unsigned ar5312_sys_frequency(void)
  283. {
  284. return ar5312_cpu_frequency() / 4;
  285. }
  286. void __init ar5312_plat_time_init(void)
  287. {
  288. mips_hpt_frequency = ar5312_cpu_frequency() / 2;
  289. }
  290. void __init ar5312_plat_mem_setup(void)
  291. {
  292. void __iomem *sdram_base;
  293. u32 memsize, memcfg, bank0_ac, bank1_ac;
  294. u32 devid;
  295. /* Detect memory size */
  296. sdram_base = ioremap(AR5312_SDRAMCTL_BASE,
  297. AR5312_SDRAMCTL_SIZE);
  298. memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
  299. bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
  300. bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
  301. memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
  302. (bank1_ac ? (1 << (bank1_ac + 1)) : 0);
  303. memsize <<= 20;
  304. memblock_add(0, memsize);
  305. iounmap(sdram_base);
  306. ar5312_rst_base = ioremap(AR5312_RST_BASE, AR5312_RST_SIZE);
  307. devid = ar5312_rst_reg_read(AR5312_REV);
  308. devid >>= AR5312_REV_WMAC_MIN_S;
  309. devid &= AR5312_REV_CHIP;
  310. ath25_board.devid = (u16)devid;
  311. /* Clear any lingering AHB errors */
  312. ar5312_rst_reg_read(AR5312_PROCADDR);
  313. ar5312_rst_reg_read(AR5312_DMAADDR);
  314. ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
  315. _machine_restart = ar5312_restart;
  316. }
  317. void __init ar5312_arch_init(void)
  318. {
  319. unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
  320. AR5312_MISC_IRQ_UART0);
  321. ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
  322. }