ar2315.c 9.4 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
  7. * Copyright (C) 2006 FON Technology, SL.
  8. * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
  9. * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  10. * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
  11. */
  12. /*
  13. * Platform devices for Atheros AR2315 SoCs
  14. */
  15. #include <linux/init.h>
  16. #include <linux/kernel.h>
  17. #include <linux/bitops.h>
  18. #include <linux/irqdomain.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/memblock.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/reboot.h>
  23. #include <asm/bootinfo.h>
  24. #include <asm/reboot.h>
  25. #include <asm/time.h>
  26. #include <ath25_platform.h>
  27. #include "devices.h"
  28. #include "ar2315.h"
  29. #include "ar2315_regs.h"
  30. static void __iomem *ar2315_rst_base;
  31. static struct irq_domain *ar2315_misc_irq_domain;
  32. static inline u32 ar2315_rst_reg_read(u32 reg)
  33. {
  34. return __raw_readl(ar2315_rst_base + reg);
  35. }
  36. static inline void ar2315_rst_reg_write(u32 reg, u32 val)
  37. {
  38. __raw_writel(val, ar2315_rst_base + reg);
  39. }
  40. static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
  41. {
  42. u32 ret = ar2315_rst_reg_read(reg);
  43. ret &= ~mask;
  44. ret |= val;
  45. ar2315_rst_reg_write(reg, ret);
  46. }
  47. static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
  48. {
  49. ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
  50. ar2315_rst_reg_read(AR2315_AHB_ERR1);
  51. pr_emerg("AHB fatal error\n");
  52. machine_restart("AHB error"); /* Catastrophic failure */
  53. return IRQ_HANDLED;
  54. }
  55. static void ar2315_misc_irq_handler(struct irq_desc *desc)
  56. {
  57. u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
  58. ar2315_rst_reg_read(AR2315_IMR);
  59. unsigned nr, misc_irq = 0;
  60. if (pending) {
  61. struct irq_domain *domain = irq_desc_get_handler_data(desc);
  62. nr = __ffs(pending);
  63. misc_irq = irq_find_mapping(domain, nr);
  64. }
  65. if (misc_irq) {
  66. if (nr == AR2315_MISC_IRQ_GPIO)
  67. ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
  68. else if (nr == AR2315_MISC_IRQ_WATCHDOG)
  69. ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
  70. generic_handle_irq(misc_irq);
  71. } else {
  72. spurious_interrupt();
  73. }
  74. }
  75. static void ar2315_misc_irq_unmask(struct irq_data *d)
  76. {
  77. ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
  78. }
  79. static void ar2315_misc_irq_mask(struct irq_data *d)
  80. {
  81. ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
  82. }
  83. static struct irq_chip ar2315_misc_irq_chip = {
  84. .name = "ar2315-misc",
  85. .irq_unmask = ar2315_misc_irq_unmask,
  86. .irq_mask = ar2315_misc_irq_mask,
  87. };
  88. static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
  89. irq_hw_number_t hw)
  90. {
  91. irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
  92. return 0;
  93. }
  94. static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
  95. .map = ar2315_misc_irq_map,
  96. };
  97. /*
  98. * Called when an interrupt is received, this function
  99. * determines exactly which interrupt it was, and it
  100. * invokes the appropriate handler.
  101. *
  102. * Implicitly, we also define interrupt priority by
  103. * choosing which to dispatch first.
  104. */
  105. static void ar2315_irq_dispatch(void)
  106. {
  107. u32 pending = read_c0_status() & read_c0_cause();
  108. if (pending & CAUSEF_IP3)
  109. do_IRQ(AR2315_IRQ_WLAN0);
  110. #ifdef CONFIG_PCI_AR2315
  111. else if (pending & CAUSEF_IP5)
  112. do_IRQ(AR2315_IRQ_LCBUS_PCI);
  113. #endif
  114. else if (pending & CAUSEF_IP2)
  115. do_IRQ(AR2315_IRQ_MISC);
  116. else if (pending & CAUSEF_IP7)
  117. do_IRQ(ATH25_IRQ_CPU_CLOCK);
  118. else
  119. spurious_interrupt();
  120. }
  121. void __init ar2315_arch_init_irq(void)
  122. {
  123. struct irq_domain *domain;
  124. unsigned irq;
  125. ath25_irq_dispatch = ar2315_irq_dispatch;
  126. domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
  127. &ar2315_misc_irq_domain_ops, NULL);
  128. if (!domain)
  129. panic("Failed to add IRQ domain");
  130. irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
  131. if (request_irq(irq, ar2315_ahb_err_handler, 0, "ar2315-ahb-error",
  132. NULL))
  133. pr_err("Failed to register ar2315-ahb-error interrupt\n");
  134. irq_set_chained_handler_and_data(AR2315_IRQ_MISC,
  135. ar2315_misc_irq_handler, domain);
  136. ar2315_misc_irq_domain = domain;
  137. }
  138. void __init ar2315_init_devices(void)
  139. {
  140. /* Find board configuration */
  141. ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
  142. ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
  143. }
  144. static void ar2315_restart(char *command)
  145. {
  146. void (*mips_reset_vec)(void) = (void *)0xbfc00000;
  147. local_irq_disable();
  148. /* try reset the system via reset control */
  149. ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
  150. /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
  151. * a workaround. Give it some time to attempt a gpio based hardware
  152. * reset (atheros reference design workaround) */
  153. /* TODO: implement the GPIO reset workaround */
  154. /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
  155. * workaround. Attempt to jump to the mips reset location -
  156. * the boot loader itself might be able to recover the system */
  157. mips_reset_vec();
  158. }
  159. /*
  160. * This table is indexed by bits 5..4 of the CLOCKCTL1 register
  161. * to determine the predevisor value.
  162. */
  163. static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
  164. static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
  165. static unsigned __init ar2315_sys_clk(u32 clock_ctl)
  166. {
  167. unsigned int pllc_ctrl, cpu_div;
  168. unsigned int pllc_out, refdiv, fdiv, divby2;
  169. unsigned int clk_div;
  170. pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
  171. refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
  172. refdiv = clockctl1_predivide_table[refdiv];
  173. fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
  174. divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
  175. pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv;
  176. /* clkm input selected */
  177. switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
  178. case 0:
  179. case 1:
  180. clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
  181. clk_div = pllc_divide_table[clk_div];
  182. break;
  183. case 2:
  184. clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
  185. clk_div = pllc_divide_table[clk_div];
  186. break;
  187. default:
  188. pllc_out = 40000000;
  189. clk_div = 1;
  190. break;
  191. }
  192. cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
  193. cpu_div = cpu_div * 2 ?: 1;
  194. return pllc_out / (clk_div * cpu_div);
  195. }
  196. static inline unsigned ar2315_cpu_frequency(void)
  197. {
  198. return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
  199. }
  200. static inline unsigned ar2315_apb_frequency(void)
  201. {
  202. return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
  203. }
  204. void __init ar2315_plat_time_init(void)
  205. {
  206. mips_hpt_frequency = ar2315_cpu_frequency() / 2;
  207. }
  208. void __init ar2315_plat_mem_setup(void)
  209. {
  210. void __iomem *sdram_base;
  211. u32 memsize, memcfg;
  212. u32 devid;
  213. u32 config;
  214. /* Detect memory size */
  215. sdram_base = ioremap(AR2315_SDRAMCTL_BASE,
  216. AR2315_SDRAMCTL_SIZE);
  217. memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
  218. memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
  219. memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
  220. memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
  221. memsize <<= 3;
  222. memblock_add(0, memsize);
  223. iounmap(sdram_base);
  224. ar2315_rst_base = ioremap(AR2315_RST_BASE, AR2315_RST_SIZE);
  225. /* Detect the hardware based on the device ID */
  226. devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
  227. switch (devid) {
  228. case 0x91: /* Need to check */
  229. ath25_soc = ATH25_SOC_AR2318;
  230. break;
  231. case 0x90:
  232. ath25_soc = ATH25_SOC_AR2317;
  233. break;
  234. case 0x87:
  235. ath25_soc = ATH25_SOC_AR2316;
  236. break;
  237. case 0x86:
  238. default:
  239. ath25_soc = ATH25_SOC_AR2315;
  240. break;
  241. }
  242. ath25_board.devid = devid;
  243. /* Clear any lingering AHB errors */
  244. config = read_c0_config();
  245. write_c0_config(config & ~0x3);
  246. ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
  247. ar2315_rst_reg_read(AR2315_AHB_ERR1);
  248. ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
  249. _machine_restart = ar2315_restart;
  250. }
  251. #ifdef CONFIG_PCI_AR2315
  252. static struct resource ar2315_pci_res[] = {
  253. {
  254. .name = "ar2315-pci-ctrl",
  255. .flags = IORESOURCE_MEM,
  256. .start = AR2315_PCI_BASE,
  257. .end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1,
  258. },
  259. {
  260. .name = "ar2315-pci-ext",
  261. .flags = IORESOURCE_MEM,
  262. .start = AR2315_PCI_EXT_BASE,
  263. .end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1,
  264. },
  265. {
  266. .name = "ar2315-pci",
  267. .flags = IORESOURCE_IRQ,
  268. .start = AR2315_IRQ_LCBUS_PCI,
  269. .end = AR2315_IRQ_LCBUS_PCI,
  270. },
  271. };
  272. #endif
  273. void __init ar2315_arch_init(void)
  274. {
  275. unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
  276. AR2315_MISC_IRQ_UART0);
  277. ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
  278. #ifdef CONFIG_PCI_AR2315
  279. if (ath25_soc == ATH25_SOC_AR2315) {
  280. /* Reset PCI DMA logic */
  281. ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
  282. msleep(20);
  283. ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
  284. msleep(20);
  285. /* Configure endians */
  286. ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
  287. AR2315_CONFIG_PCIAHB_BRIDGE);
  288. /* Configure as PCI host with DMA */
  289. ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
  290. (AR2315_PCICLK_IN_FREQ_DIV_6 <<
  291. AR2315_PCICLK_DIV_S));
  292. ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
  293. ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |
  294. AR2315_IF_MASK, AR2315_IF_PCI |
  295. AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
  296. (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
  297. AR2315_IF_PCI_CLK_SHIFT));
  298. platform_device_register_simple("ar2315-pci", -1,
  299. ar2315_pci_res,
  300. ARRAY_SIZE(ar2315_pci_res));
  301. }
  302. #endif
  303. }