gpio.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
  4. * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
  5. * Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org>
  6. */
  7. #include <linux/init.h>
  8. #include <linux/export.h>
  9. #include <linux/gpio.h>
  10. #include <asm/mach-ar7/ar7.h>
  11. #define AR7_GPIO_MAX 32
  12. #define TITAN_GPIO_MAX 51
  13. struct ar7_gpio_chip {
  14. void __iomem *regs;
  15. struct gpio_chip chip;
  16. };
  17. static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
  18. {
  19. struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
  20. void __iomem *gpio_in = gpch->regs + AR7_GPIO_INPUT;
  21. return !!(readl(gpio_in) & (1 << gpio));
  22. }
  23. static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
  24. {
  25. struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
  26. void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0;
  27. void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1;
  28. return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
  29. }
  30. static void ar7_gpio_set_value(struct gpio_chip *chip,
  31. unsigned gpio, int value)
  32. {
  33. struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
  34. void __iomem *gpio_out = gpch->regs + AR7_GPIO_OUTPUT;
  35. unsigned tmp;
  36. tmp = readl(gpio_out) & ~(1 << gpio);
  37. if (value)
  38. tmp |= 1 << gpio;
  39. writel(tmp, gpio_out);
  40. }
  41. static void titan_gpio_set_value(struct gpio_chip *chip,
  42. unsigned gpio, int value)
  43. {
  44. struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
  45. void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0;
  46. void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1;
  47. unsigned tmp;
  48. tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
  49. if (value)
  50. tmp |= 1 << (gpio & 0x1f);
  51. writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
  52. }
  53. static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
  54. {
  55. struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
  56. void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
  57. writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
  58. return 0;
  59. }
  60. static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
  61. {
  62. struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
  63. void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
  64. void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
  65. if (gpio >= TITAN_GPIO_MAX)
  66. return -EINVAL;
  67. writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
  68. gpio >> 5 ? gpio_dir1 : gpio_dir0);
  69. return 0;
  70. }
  71. static int ar7_gpio_direction_output(struct gpio_chip *chip,
  72. unsigned gpio, int value)
  73. {
  74. struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
  75. void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
  76. ar7_gpio_set_value(chip, gpio, value);
  77. writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
  78. return 0;
  79. }
  80. static int titan_gpio_direction_output(struct gpio_chip *chip,
  81. unsigned gpio, int value)
  82. {
  83. struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
  84. void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
  85. void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
  86. if (gpio >= TITAN_GPIO_MAX)
  87. return -EINVAL;
  88. titan_gpio_set_value(chip, gpio, value);
  89. writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
  90. (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
  91. return 0;
  92. }
  93. static struct ar7_gpio_chip ar7_gpio_chip = {
  94. .chip = {
  95. .label = "ar7-gpio",
  96. .direction_input = ar7_gpio_direction_input,
  97. .direction_output = ar7_gpio_direction_output,
  98. .set = ar7_gpio_set_value,
  99. .get = ar7_gpio_get_value,
  100. .base = 0,
  101. .ngpio = AR7_GPIO_MAX,
  102. }
  103. };
  104. static struct ar7_gpio_chip titan_gpio_chip = {
  105. .chip = {
  106. .label = "titan-gpio",
  107. .direction_input = titan_gpio_direction_input,
  108. .direction_output = titan_gpio_direction_output,
  109. .set = titan_gpio_set_value,
  110. .get = titan_gpio_get_value,
  111. .base = 0,
  112. .ngpio = TITAN_GPIO_MAX,
  113. }
  114. };
  115. static inline int ar7_gpio_enable_ar7(unsigned gpio)
  116. {
  117. void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
  118. writel(readl(gpio_en) | (1 << gpio), gpio_en);
  119. return 0;
  120. }
  121. static inline int ar7_gpio_enable_titan(unsigned gpio)
  122. {
  123. void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
  124. void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
  125. writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
  126. gpio >> 5 ? gpio_en1 : gpio_en0);
  127. return 0;
  128. }
  129. int ar7_gpio_enable(unsigned gpio)
  130. {
  131. return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
  132. ar7_gpio_enable_ar7(gpio);
  133. }
  134. EXPORT_SYMBOL(ar7_gpio_enable);
  135. static inline int ar7_gpio_disable_ar7(unsigned gpio)
  136. {
  137. void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
  138. writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
  139. return 0;
  140. }
  141. static inline int ar7_gpio_disable_titan(unsigned gpio)
  142. {
  143. void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
  144. void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
  145. writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
  146. gpio >> 5 ? gpio_en1 : gpio_en0);
  147. return 0;
  148. }
  149. int ar7_gpio_disable(unsigned gpio)
  150. {
  151. return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
  152. ar7_gpio_disable_ar7(gpio);
  153. }
  154. EXPORT_SYMBOL(ar7_gpio_disable);
  155. struct titan_gpio_cfg {
  156. u32 reg;
  157. u32 shift;
  158. u32 func;
  159. };
  160. static const struct titan_gpio_cfg titan_gpio_table[] = {
  161. /* reg, start bit, mux value */
  162. {4, 24, 1},
  163. {4, 26, 1},
  164. {4, 28, 1},
  165. {4, 30, 1},
  166. {5, 6, 1},
  167. {5, 8, 1},
  168. {5, 10, 1},
  169. {5, 12, 1},
  170. {7, 14, 3},
  171. {7, 16, 3},
  172. {7, 18, 3},
  173. {7, 20, 3},
  174. {7, 22, 3},
  175. {7, 26, 3},
  176. {7, 28, 3},
  177. {7, 30, 3},
  178. {8, 0, 3},
  179. {8, 2, 3},
  180. {8, 4, 3},
  181. {8, 10, 3},
  182. {8, 14, 3},
  183. {8, 16, 3},
  184. {8, 18, 3},
  185. {8, 20, 3},
  186. {9, 8, 3},
  187. {9, 10, 3},
  188. {9, 12, 3},
  189. {9, 14, 3},
  190. {9, 18, 3},
  191. {9, 20, 3},
  192. {9, 24, 3},
  193. {9, 26, 3},
  194. {9, 28, 3},
  195. {9, 30, 3},
  196. {10, 0, 3},
  197. {10, 2, 3},
  198. {10, 8, 3},
  199. {10, 10, 3},
  200. {10, 12, 3},
  201. {10, 14, 3},
  202. {13, 12, 3},
  203. {13, 14, 3},
  204. {13, 16, 3},
  205. {13, 18, 3},
  206. {13, 24, 3},
  207. {13, 26, 3},
  208. {13, 28, 3},
  209. {13, 30, 3},
  210. {14, 2, 3},
  211. {14, 6, 3},
  212. {14, 8, 3},
  213. {14, 12, 3}
  214. };
  215. static int titan_gpio_pinsel(unsigned gpio)
  216. {
  217. struct titan_gpio_cfg gpio_cfg;
  218. u32 mux_status, pin_sel_reg, tmp;
  219. void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL);
  220. if (gpio >= ARRAY_SIZE(titan_gpio_table))
  221. return -EINVAL;
  222. gpio_cfg = titan_gpio_table[gpio];
  223. pin_sel_reg = gpio_cfg.reg - 1;
  224. mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3;
  225. /* Check the mux status */
  226. if (!((mux_status == 0) || (mux_status == gpio_cfg.func)))
  227. return 0;
  228. /* Set the pin sel value */
  229. tmp = readl(pin_sel + pin_sel_reg);
  230. tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
  231. writel(tmp, pin_sel + pin_sel_reg);
  232. return 0;
  233. }
  234. /* Perform minimal Titan GPIO configuration */
  235. static void titan_gpio_init(void)
  236. {
  237. unsigned i;
  238. for (i = 44; i < 48; i++) {
  239. titan_gpio_pinsel(i);
  240. ar7_gpio_enable_titan(i);
  241. titan_gpio_direction_input(&titan_gpio_chip.chip, i);
  242. }
  243. }
  244. int __init ar7_gpio_init(void)
  245. {
  246. int ret;
  247. struct ar7_gpio_chip *gpch;
  248. unsigned size;
  249. if (!ar7_is_titan()) {
  250. gpch = &ar7_gpio_chip;
  251. size = 0x10;
  252. } else {
  253. gpch = &titan_gpio_chip;
  254. size = 0x1f;
  255. }
  256. gpch->regs = ioremap(AR7_REGS_GPIO, size);
  257. if (!gpch->regs) {
  258. printk(KERN_ERR "%s: failed to ioremap regs\n",
  259. gpch->chip.label);
  260. return -ENOMEM;
  261. }
  262. ret = gpiochip_add_data(&gpch->chip, gpch);
  263. if (ret) {
  264. printk(KERN_ERR "%s: failed to add gpiochip\n",
  265. gpch->chip.label);
  266. return ret;
  267. }
  268. printk(KERN_INFO "%s: registered %d GPIOs\n",
  269. gpch->chip.label, gpch->chip.ngpio);
  270. if (ar7_is_titan())
  271. titan_gpio_init();
  272. return ret;
  273. }