clock.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
  4. * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
  5. * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/init.h>
  9. #include <linux/types.h>
  10. #include <linux/export.h>
  11. #include <linux/delay.h>
  12. #include <linux/gcd.h>
  13. #include <linux/io.h>
  14. #include <linux/err.h>
  15. #include <linux/clk.h>
  16. #include <asm/addrspace.h>
  17. #include <asm/mach-ar7/ar7.h>
  18. #define BOOT_PLL_SOURCE_MASK 0x3
  19. #define CPU_PLL_SOURCE_SHIFT 16
  20. #define BUS_PLL_SOURCE_SHIFT 14
  21. #define USB_PLL_SOURCE_SHIFT 18
  22. #define DSP_PLL_SOURCE_SHIFT 22
  23. #define BOOT_PLL_SOURCE_AFE 0
  24. #define BOOT_PLL_SOURCE_BUS 0
  25. #define BOOT_PLL_SOURCE_REF 1
  26. #define BOOT_PLL_SOURCE_XTAL 2
  27. #define BOOT_PLL_SOURCE_CPU 3
  28. #define BOOT_PLL_BYPASS 0x00000020
  29. #define BOOT_PLL_ASYNC_MODE 0x02000000
  30. #define BOOT_PLL_2TO1_MODE 0x00008000
  31. #define TNETD7200_CLOCK_ID_CPU 0
  32. #define TNETD7200_CLOCK_ID_DSP 1
  33. #define TNETD7200_CLOCK_ID_USB 2
  34. #define TNETD7200_DEF_CPU_CLK 211000000
  35. #define TNETD7200_DEF_DSP_CLK 125000000
  36. #define TNETD7200_DEF_USB_CLK 48000000
  37. struct tnetd7300_clock {
  38. u32 ctrl;
  39. #define PREDIV_MASK 0x001f0000
  40. #define PREDIV_SHIFT 16
  41. #define POSTDIV_MASK 0x0000001f
  42. u32 unused1[3];
  43. u32 pll;
  44. #define MUL_MASK 0x0000f000
  45. #define MUL_SHIFT 12
  46. #define PLL_MODE_MASK 0x00000001
  47. #define PLL_NDIV 0x00000800
  48. #define PLL_DIV 0x00000002
  49. #define PLL_STATUS 0x00000001
  50. u32 unused2[3];
  51. };
  52. struct tnetd7300_clocks {
  53. struct tnetd7300_clock bus;
  54. struct tnetd7300_clock cpu;
  55. struct tnetd7300_clock usb;
  56. struct tnetd7300_clock dsp;
  57. };
  58. struct tnetd7200_clock {
  59. u32 ctrl;
  60. u32 unused1[3];
  61. #define DIVISOR_ENABLE_MASK 0x00008000
  62. u32 mul;
  63. u32 prediv;
  64. u32 postdiv;
  65. u32 postdiv2;
  66. u32 unused2[6];
  67. u32 cmd;
  68. u32 status;
  69. u32 cmden;
  70. u32 padding[15];
  71. };
  72. struct tnetd7200_clocks {
  73. struct tnetd7200_clock cpu;
  74. struct tnetd7200_clock dsp;
  75. struct tnetd7200_clock usb;
  76. };
  77. static struct clk bus_clk = {
  78. .rate = 125000000,
  79. };
  80. static struct clk cpu_clk = {
  81. .rate = 150000000,
  82. };
  83. static struct clk dsp_clk;
  84. static struct clk vbus_clk;
  85. static void approximate(int base, int target, int *prediv,
  86. int *postdiv, int *mul)
  87. {
  88. int i, j, k, freq, res = target;
  89. for (i = 1; i <= 16; i++)
  90. for (j = 1; j <= 32; j++)
  91. for (k = 1; k <= 32; k++) {
  92. freq = abs(base / j * i / k - target);
  93. if (freq < res) {
  94. res = freq;
  95. *mul = i;
  96. *prediv = j;
  97. *postdiv = k;
  98. }
  99. }
  100. }
  101. static void calculate(int base, int target, int *prediv, int *postdiv,
  102. int *mul)
  103. {
  104. int tmp_gcd, tmp_base, tmp_freq;
  105. for (*prediv = 1; *prediv <= 32; (*prediv)++) {
  106. tmp_base = base / *prediv;
  107. tmp_gcd = gcd(target, tmp_base);
  108. *mul = target / tmp_gcd;
  109. *postdiv = tmp_base / tmp_gcd;
  110. if ((*mul < 1) || (*mul >= 16))
  111. continue;
  112. if ((*postdiv > 0) & (*postdiv <= 32))
  113. break;
  114. }
  115. if (base / *prediv * *mul / *postdiv != target) {
  116. approximate(base, target, prediv, postdiv, mul);
  117. tmp_freq = base / *prediv * *mul / *postdiv;
  118. printk(KERN_WARNING
  119. "Adjusted requested frequency %d to %d\n",
  120. target, tmp_freq);
  121. }
  122. printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
  123. *prediv, *postdiv, *mul);
  124. }
  125. static int tnetd7300_dsp_clock(void)
  126. {
  127. u32 didr1, didr2;
  128. u8 rev = ar7_chip_rev();
  129. didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
  130. didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
  131. if (didr2 & (1 << 23))
  132. return 0;
  133. if ((rev >= 0x23) && (rev != 0x57))
  134. return 250000000;
  135. if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
  136. > 4208000)
  137. return 250000000;
  138. return 0;
  139. }
  140. static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
  141. u32 *bootcr, u32 bus_clock)
  142. {
  143. int product;
  144. int base_clock = AR7_REF_CLOCK;
  145. u32 ctrl = readl(&clock->ctrl);
  146. u32 pll = readl(&clock->pll);
  147. int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
  148. int postdiv = (ctrl & POSTDIV_MASK) + 1;
  149. int divisor = prediv * postdiv;
  150. int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
  151. switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
  152. case BOOT_PLL_SOURCE_BUS:
  153. base_clock = bus_clock;
  154. break;
  155. case BOOT_PLL_SOURCE_REF:
  156. base_clock = AR7_REF_CLOCK;
  157. break;
  158. case BOOT_PLL_SOURCE_XTAL:
  159. base_clock = AR7_XTAL_CLOCK;
  160. break;
  161. case BOOT_PLL_SOURCE_CPU:
  162. base_clock = cpu_clk.rate;
  163. break;
  164. }
  165. if (*bootcr & BOOT_PLL_BYPASS)
  166. return base_clock / divisor;
  167. if ((pll & PLL_MODE_MASK) == 0)
  168. return (base_clock >> (mul / 16 + 1)) / divisor;
  169. if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
  170. product = (mul & 1) ?
  171. (base_clock * mul) >> 1 :
  172. (base_clock * (mul - 1)) >> 2;
  173. return product / divisor;
  174. }
  175. if (mul == 16)
  176. return base_clock / divisor;
  177. return base_clock * mul / divisor;
  178. }
  179. static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
  180. u32 *bootcr, u32 frequency)
  181. {
  182. int prediv, postdiv, mul;
  183. int base_clock = bus_clk.rate;
  184. switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
  185. case BOOT_PLL_SOURCE_BUS:
  186. base_clock = bus_clk.rate;
  187. break;
  188. case BOOT_PLL_SOURCE_REF:
  189. base_clock = AR7_REF_CLOCK;
  190. break;
  191. case BOOT_PLL_SOURCE_XTAL:
  192. base_clock = AR7_XTAL_CLOCK;
  193. break;
  194. case BOOT_PLL_SOURCE_CPU:
  195. base_clock = cpu_clk.rate;
  196. break;
  197. }
  198. calculate(base_clock, frequency, &prediv, &postdiv, &mul);
  199. writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
  200. mdelay(1);
  201. writel(4, &clock->pll);
  202. while (readl(&clock->pll) & PLL_STATUS)
  203. ;
  204. writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
  205. mdelay(75);
  206. }
  207. static void __init tnetd7300_init_clocks(void)
  208. {
  209. u32 *bootcr = (u32 *)ioremap(AR7_REGS_DCL, 4);
  210. struct tnetd7300_clocks *clocks =
  211. ioremap(UR8_REGS_CLOCKS,
  212. sizeof(struct tnetd7300_clocks));
  213. bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
  214. &clocks->bus, bootcr, AR7_AFE_CLOCK);
  215. if (*bootcr & BOOT_PLL_ASYNC_MODE)
  216. cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
  217. &clocks->cpu, bootcr, AR7_AFE_CLOCK);
  218. else
  219. cpu_clk.rate = bus_clk.rate;
  220. if (dsp_clk.rate == 250000000)
  221. tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
  222. bootcr, dsp_clk.rate);
  223. iounmap(clocks);
  224. iounmap(bootcr);
  225. }
  226. static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
  227. int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
  228. {
  229. printk(KERN_INFO
  230. "Clocks: base = %d, frequency = %u, prediv = %d, "
  231. "postdiv = %d, postdiv2 = %d, mul = %d\n",
  232. base, frequency, prediv, postdiv, postdiv2, mul);
  233. writel(0, &clock->ctrl);
  234. writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv);
  235. writel((mul - 1) & 0xF, &clock->mul);
  236. while (readl(&clock->status) & 0x1)
  237. ; /* nop */
  238. writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv);
  239. writel(readl(&clock->cmden) | 1, &clock->cmden);
  240. writel(readl(&clock->cmd) | 1, &clock->cmd);
  241. while (readl(&clock->status) & 0x1)
  242. ; /* nop */
  243. writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2);
  244. writel(readl(&clock->cmden) | 1, &clock->cmden);
  245. writel(readl(&clock->cmd) | 1, &clock->cmd);
  246. while (readl(&clock->status) & 0x1)
  247. ; /* nop */
  248. writel(readl(&clock->ctrl) | 1, &clock->ctrl);
  249. }
  250. static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
  251. {
  252. if (*bootcr & BOOT_PLL_ASYNC_MODE)
  253. /* Async */
  254. switch (clock_id) {
  255. case TNETD7200_CLOCK_ID_DSP:
  256. return AR7_REF_CLOCK;
  257. default:
  258. return AR7_AFE_CLOCK;
  259. }
  260. else
  261. /* Sync */
  262. if (*bootcr & BOOT_PLL_2TO1_MODE)
  263. /* 2:1 */
  264. switch (clock_id) {
  265. case TNETD7200_CLOCK_ID_DSP:
  266. return AR7_REF_CLOCK;
  267. default:
  268. return AR7_AFE_CLOCK;
  269. }
  270. else
  271. /* 1:1 */
  272. return AR7_REF_CLOCK;
  273. }
  274. static void __init tnetd7200_init_clocks(void)
  275. {
  276. u32 *bootcr = (u32 *)ioremap(AR7_REGS_DCL, 4);
  277. struct tnetd7200_clocks *clocks =
  278. ioremap(AR7_REGS_CLOCKS,
  279. sizeof(struct tnetd7200_clocks));
  280. int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
  281. int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
  282. int usb_base, usb_mul, usb_prediv, usb_postdiv;
  283. cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
  284. dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
  285. if (*bootcr & BOOT_PLL_ASYNC_MODE) {
  286. printk(KERN_INFO "Clocks: Async mode\n");
  287. printk(KERN_INFO "Clocks: Setting DSP clock\n");
  288. calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
  289. &dsp_prediv, &dsp_postdiv, &dsp_mul);
  290. bus_clk.rate =
  291. ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
  292. tnetd7200_set_clock(dsp_base, &clocks->dsp,
  293. dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
  294. bus_clk.rate);
  295. printk(KERN_INFO "Clocks: Setting CPU clock\n");
  296. calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
  297. &cpu_postdiv, &cpu_mul);
  298. cpu_clk.rate =
  299. ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
  300. tnetd7200_set_clock(cpu_base, &clocks->cpu,
  301. cpu_prediv, cpu_postdiv, -1, cpu_mul,
  302. cpu_clk.rate);
  303. } else
  304. if (*bootcr & BOOT_PLL_2TO1_MODE) {
  305. printk(KERN_INFO "Clocks: Sync 2:1 mode\n");
  306. printk(KERN_INFO "Clocks: Setting CPU clock\n");
  307. calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
  308. &cpu_postdiv, &cpu_mul);
  309. cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul)
  310. / cpu_postdiv;
  311. tnetd7200_set_clock(cpu_base, &clocks->cpu,
  312. cpu_prediv, cpu_postdiv, -1, cpu_mul,
  313. cpu_clk.rate);
  314. printk(KERN_INFO "Clocks: Setting DSP clock\n");
  315. calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
  316. &dsp_postdiv, &dsp_mul);
  317. bus_clk.rate = cpu_clk.rate / 2;
  318. tnetd7200_set_clock(dsp_base, &clocks->dsp,
  319. dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
  320. dsp_mul * 2, bus_clk.rate);
  321. } else {
  322. printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
  323. printk(KERN_INFO "Clocks: Setting DSP clock\n");
  324. calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
  325. &dsp_postdiv, &dsp_mul);
  326. bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul)
  327. / dsp_postdiv;
  328. tnetd7200_set_clock(dsp_base, &clocks->dsp,
  329. dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
  330. dsp_mul * 2, bus_clk.rate);
  331. cpu_clk.rate = bus_clk.rate;
  332. }
  333. printk(KERN_INFO "Clocks: Setting USB clock\n");
  334. usb_base = bus_clk.rate;
  335. calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
  336. &usb_postdiv, &usb_mul);
  337. tnetd7200_set_clock(usb_base, &clocks->usb,
  338. usb_prediv, usb_postdiv, -1, usb_mul,
  339. TNETD7200_DEF_USB_CLK);
  340. dsp_clk.rate = cpu_clk.rate;
  341. iounmap(clocks);
  342. iounmap(bootcr);
  343. }
  344. /*
  345. * Linux clock API
  346. */
  347. int clk_enable(struct clk *clk)
  348. {
  349. return 0;
  350. }
  351. EXPORT_SYMBOL(clk_enable);
  352. void clk_disable(struct clk *clk)
  353. {
  354. }
  355. EXPORT_SYMBOL(clk_disable);
  356. unsigned long clk_get_rate(struct clk *clk)
  357. {
  358. if (!clk)
  359. return 0;
  360. return clk->rate;
  361. }
  362. EXPORT_SYMBOL(clk_get_rate);
  363. struct clk *clk_get(struct device *dev, const char *id)
  364. {
  365. if (!strcmp(id, "bus"))
  366. return &bus_clk;
  367. /* cpmac and vbus share the same rate */
  368. if (!strcmp(id, "cpmac"))
  369. return &vbus_clk;
  370. if (!strcmp(id, "cpu"))
  371. return &cpu_clk;
  372. if (!strcmp(id, "dsp"))
  373. return &dsp_clk;
  374. if (!strcmp(id, "vbus"))
  375. return &vbus_clk;
  376. return ERR_PTR(-ENOENT);
  377. }
  378. EXPORT_SYMBOL(clk_get);
  379. void clk_put(struct clk *clk)
  380. {
  381. }
  382. EXPORT_SYMBOL(clk_put);
  383. void __init ar7_init_clocks(void)
  384. {
  385. switch (ar7_chip_id()) {
  386. case AR7_CHIP_7100:
  387. case AR7_CHIP_7200:
  388. tnetd7200_init_clocks();
  389. break;
  390. case AR7_CHIP_7300:
  391. dsp_clk.rate = tnetd7300_dsp_clock();
  392. tnetd7300_init_clocks();
  393. break;
  394. default:
  395. break;
  396. }
  397. /* adjust vbus clock rate */
  398. vbus_clk.rate = bus_clk.rate / 2;
  399. }
  400. /* dummy functions, should not be called */
  401. long clk_round_rate(struct clk *clk, unsigned long rate)
  402. {
  403. WARN_ON(clk);
  404. return 0;
  405. }
  406. EXPORT_SYMBOL(clk_round_rate);
  407. int clk_set_rate(struct clk *clk, unsigned long rate)
  408. {
  409. WARN_ON(clk);
  410. return 0;
  411. }
  412. EXPORT_SYMBOL(clk_set_rate);
  413. int clk_set_parent(struct clk *clk, struct clk *parent)
  414. {
  415. WARN_ON(clk);
  416. return 0;
  417. }
  418. EXPORT_SYMBOL(clk_set_parent);
  419. struct clk *clk_get_parent(struct clk *clk)
  420. {
  421. WARN_ON(clk);
  422. return NULL;
  423. }
  424. EXPORT_SYMBOL(clk_get_parent);