hw_exception_handler.S 34 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Exception handling for Microblaze
  4. *
  5. * Rewriten interrupt handling
  6. *
  7. * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
  8. * Copyright (C) 2008-2009 PetaLogix
  9. *
  10. * uClinux customisation (C) 2005 John Williams
  11. *
  12. * MMU code derived from arch/ppc/kernel/head_4xx.S:
  13. * Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org>
  14. * Initial PowerPC version.
  15. * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
  16. * Rewritten for PReP
  17. * Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
  18. * Low-level exception handers, MMU support, and rewrite.
  19. * Copyright (C) 1997 Dan Malek <dmalek@jlc.net>
  20. * PowerPC 8xx modifications.
  21. * Copyright (C) 1998-1999 TiVo, Inc.
  22. * PowerPC 403GCX modifications.
  23. * Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu>
  24. * PowerPC 403GCX/405GP modifications.
  25. * Copyright 2000 MontaVista Software Inc.
  26. * PPC405 modifications
  27. * PowerPC 403GCX/405GP modifications.
  28. * Author: MontaVista Software, Inc.
  29. * frank_rowand@mvista.com or source@mvista.com
  30. * debbie_chu@mvista.com
  31. *
  32. * Original code
  33. * Copyright (C) 2004 Xilinx, Inc.
  34. */
  35. /*
  36. * Here are the handlers which don't require enabling translation
  37. * and calling other kernel code thus we can keep their design very simple
  38. * and do all processing in real mode. All what they need is a valid current
  39. * (that is an issue for the CONFIG_REGISTER_TASK_PTR case)
  40. * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore
  41. * these registers are saved/restored
  42. * The handlers which require translation are in entry.S --KAA
  43. *
  44. * Microblaze HW Exception Handler
  45. * - Non self-modifying exception handler for the following exception conditions
  46. * - Unalignment
  47. * - Instruction bus error
  48. * - Data bus error
  49. * - Illegal instruction opcode
  50. * - Divide-by-zero
  51. *
  52. * - Privileged instruction exception (MMU)
  53. * - Data storage exception (MMU)
  54. * - Instruction storage exception (MMU)
  55. * - Data TLB miss exception (MMU)
  56. * - Instruction TLB miss exception (MMU)
  57. *
  58. * Note we disable interrupts during exception handling, otherwise we will
  59. * possibly get multiple re-entrancy if interrupt handles themselves cause
  60. * exceptions. JW
  61. */
  62. #include <asm/exceptions.h>
  63. #include <asm/unistd.h>
  64. #include <asm/page.h>
  65. #include <asm/entry.h>
  66. #include <asm/current.h>
  67. #include <linux/linkage.h>
  68. #include <linux/pgtable.h>
  69. #include <asm/mmu.h>
  70. #include <asm/signal.h>
  71. #include <asm/registers.h>
  72. #include <asm/asm-offsets.h>
  73. #undef DEBUG
  74. /* Helpful Macros */
  75. #define NUM_TO_REG(num) r ## num
  76. #ifdef CONFIG_MMU
  77. #define RESTORE_STATE \
  78. lwi r5, r1, 0; \
  79. mts rmsr, r5; \
  80. nop; \
  81. lwi r3, r1, PT_R3; \
  82. lwi r4, r1, PT_R4; \
  83. lwi r5, r1, PT_R5; \
  84. lwi r6, r1, PT_R6; \
  85. lwi r11, r1, PT_R11; \
  86. lwi r31, r1, PT_R31; \
  87. lwi r1, r1, PT_R1;
  88. #endif /* CONFIG_MMU */
  89. #define LWREG_NOP \
  90. bri ex_handler_unhandled; \
  91. nop;
  92. #define SWREG_NOP \
  93. bri ex_handler_unhandled; \
  94. nop;
  95. /* FIXME this is weird - for noMMU kernel is not possible to use brid
  96. * instruction which can shorten executed time
  97. */
  98. /* r3 is the source */
  99. #define R3_TO_LWREG_V(regnum) \
  100. swi r3, r1, 4 * regnum; \
  101. bri ex_handler_done;
  102. /* r3 is the source */
  103. #define R3_TO_LWREG(regnum) \
  104. or NUM_TO_REG (regnum), r0, r3; \
  105. bri ex_handler_done;
  106. /* r3 is the target */
  107. #define SWREG_TO_R3_V(regnum) \
  108. lwi r3, r1, 4 * regnum; \
  109. bri ex_sw_tail;
  110. /* r3 is the target */
  111. #define SWREG_TO_R3(regnum) \
  112. or r3, r0, NUM_TO_REG (regnum); \
  113. bri ex_sw_tail;
  114. #ifdef CONFIG_MMU
  115. #define R3_TO_LWREG_VM_V(regnum) \
  116. brid ex_lw_end_vm; \
  117. swi r3, r7, 4 * regnum;
  118. #define R3_TO_LWREG_VM(regnum) \
  119. brid ex_lw_end_vm; \
  120. or NUM_TO_REG (regnum), r0, r3;
  121. #define SWREG_TO_R3_VM_V(regnum) \
  122. brid ex_sw_tail_vm; \
  123. lwi r3, r7, 4 * regnum;
  124. #define SWREG_TO_R3_VM(regnum) \
  125. brid ex_sw_tail_vm; \
  126. or r3, r0, NUM_TO_REG (regnum);
  127. /* Shift right instruction depending on available configuration */
  128. #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL == 0
  129. /* Only the used shift constants defined here - add more if needed */
  130. #define BSRLI2(rD, rA) \
  131. srl rD, rA; /* << 1 */ \
  132. srl rD, rD; /* << 2 */
  133. #define BSRLI4(rD, rA) \
  134. BSRLI2(rD, rA); \
  135. BSRLI2(rD, rD)
  136. #define BSRLI10(rD, rA) \
  137. srl rD, rA; /* << 1 */ \
  138. srl rD, rD; /* << 2 */ \
  139. srl rD, rD; /* << 3 */ \
  140. srl rD, rD; /* << 4 */ \
  141. srl rD, rD; /* << 5 */ \
  142. srl rD, rD; /* << 6 */ \
  143. srl rD, rD; /* << 7 */ \
  144. srl rD, rD; /* << 8 */ \
  145. srl rD, rD; /* << 9 */ \
  146. srl rD, rD /* << 10 */
  147. #define BSRLI20(rD, rA) \
  148. BSRLI10(rD, rA); \
  149. BSRLI10(rD, rD)
  150. .macro bsrli, rD, rA, IMM
  151. .if (\IMM) == 2
  152. BSRLI2(\rD, \rA)
  153. .elseif (\IMM) == 10
  154. BSRLI10(\rD, \rA)
  155. .elseif (\IMM) == 12
  156. BSRLI2(\rD, \rA)
  157. BSRLI10(\rD, \rD)
  158. .elseif (\IMM) == 14
  159. BSRLI4(\rD, \rA)
  160. BSRLI10(\rD, \rD)
  161. .elseif (\IMM) == 20
  162. BSRLI20(\rD, \rA)
  163. .elseif (\IMM) == 24
  164. BSRLI4(\rD, \rA)
  165. BSRLI20(\rD, \rD)
  166. .elseif (\IMM) == 28
  167. BSRLI4(\rD, \rA)
  168. BSRLI4(\rD, \rD)
  169. BSRLI20(\rD, \rD)
  170. .else
  171. .error "BSRLI shift macros \IMM"
  172. .endif
  173. .endm
  174. #endif
  175. #endif /* CONFIG_MMU */
  176. .extern other_exception_handler /* Defined in exception.c */
  177. /*
  178. * hw_exception_handler - Handler for exceptions
  179. *
  180. * Exception handler notes:
  181. * - Handles all exceptions
  182. * - Does not handle unaligned exceptions during load into r17, r1, r0.
  183. * - Does not handle unaligned exceptions during store from r17 (cannot be
  184. * done) and r1 (slows down common case)
  185. *
  186. * Relevant register structures
  187. *
  188. * EAR - |----|----|----|----|----|----|----|----|
  189. * - < ## 32 bit faulting address ## >
  190. *
  191. * ESR - |----|----|----|----|----| - | - |-----|-----|
  192. * - W S REG EXC
  193. *
  194. *
  195. * STACK FRAME STRUCTURE (for CONFIG_MMU=n)
  196. * ----------------------------------------
  197. *
  198. * +-------------+ + 0
  199. * | MSR |
  200. * +-------------+ + 4
  201. * | r1 |
  202. * | . |
  203. * | . |
  204. * | . |
  205. * | . |
  206. * | r18 |
  207. * +-------------+ + 76
  208. * | . |
  209. * | . |
  210. *
  211. * MMU kernel uses the same 'pt_pool_space' pointed space
  212. * which is used for storing register values - noMMu style was, that values were
  213. * stored in stack but in case of failure you lost information about register.
  214. * Currently you can see register value in memory in specific place.
  215. * In compare to with previous solution the speed should be the same.
  216. *
  217. * MMU exception handler has different handling compare to no MMU kernel.
  218. * Exception handler use jump table for directing of what happen. For MMU kernel
  219. * is this approach better because MMU relate exception are handled by asm code
  220. * in this file. In compare to with MMU expect of unaligned exception
  221. * is everything handled by C code.
  222. */
  223. /*
  224. * every of these handlers is entered having R3/4/5/6/11/current saved on stack
  225. * and clobbered so care should be taken to restore them if someone is going to
  226. * return from exception
  227. */
  228. /* wrappers to restore state before coming to entry.S */
  229. #ifdef CONFIG_MMU
  230. .section .data
  231. .align 4
  232. pt_pool_space:
  233. .space PT_SIZE
  234. #ifdef DEBUG
  235. /* Create space for exception counting. */
  236. .section .data
  237. .global exception_debug_table
  238. .align 4
  239. exception_debug_table:
  240. /* Look at exception vector table. There is 32 exceptions * word size */
  241. .space (32 * 4)
  242. #endif /* DEBUG */
  243. .section .rodata
  244. .align 4
  245. _MB_HW_ExceptionVectorTable:
  246. /* 0 - Undefined */
  247. .long TOPHYS(ex_handler_unhandled)
  248. /* 1 - Unaligned data access exception */
  249. .long TOPHYS(handle_unaligned_ex)
  250. /* 2 - Illegal op-code exception */
  251. .long TOPHYS(full_exception_trapw)
  252. /* 3 - Instruction bus error exception */
  253. .long TOPHYS(full_exception_trapw)
  254. /* 4 - Data bus error exception */
  255. .long TOPHYS(full_exception_trapw)
  256. /* 5 - Divide by zero exception */
  257. .long TOPHYS(full_exception_trapw)
  258. /* 6 - Floating point unit exception */
  259. .long TOPHYS(full_exception_trapw)
  260. /* 7 - Privileged instruction exception */
  261. .long TOPHYS(full_exception_trapw)
  262. /* 8 - 15 - Undefined */
  263. .long TOPHYS(ex_handler_unhandled)
  264. .long TOPHYS(ex_handler_unhandled)
  265. .long TOPHYS(ex_handler_unhandled)
  266. .long TOPHYS(ex_handler_unhandled)
  267. .long TOPHYS(ex_handler_unhandled)
  268. .long TOPHYS(ex_handler_unhandled)
  269. .long TOPHYS(ex_handler_unhandled)
  270. .long TOPHYS(ex_handler_unhandled)
  271. /* 16 - Data storage exception */
  272. .long TOPHYS(handle_data_storage_exception)
  273. /* 17 - Instruction storage exception */
  274. .long TOPHYS(handle_instruction_storage_exception)
  275. /* 18 - Data TLB miss exception */
  276. .long TOPHYS(handle_data_tlb_miss_exception)
  277. /* 19 - Instruction TLB miss exception */
  278. .long TOPHYS(handle_instruction_tlb_miss_exception)
  279. /* 20 - 31 - Undefined */
  280. .long TOPHYS(ex_handler_unhandled)
  281. .long TOPHYS(ex_handler_unhandled)
  282. .long TOPHYS(ex_handler_unhandled)
  283. .long TOPHYS(ex_handler_unhandled)
  284. .long TOPHYS(ex_handler_unhandled)
  285. .long TOPHYS(ex_handler_unhandled)
  286. .long TOPHYS(ex_handler_unhandled)
  287. .long TOPHYS(ex_handler_unhandled)
  288. .long TOPHYS(ex_handler_unhandled)
  289. .long TOPHYS(ex_handler_unhandled)
  290. .long TOPHYS(ex_handler_unhandled)
  291. .long TOPHYS(ex_handler_unhandled)
  292. #endif
  293. .global _hw_exception_handler
  294. .section .text
  295. .align 4
  296. .ent _hw_exception_handler
  297. _hw_exception_handler:
  298. #ifndef CONFIG_MMU
  299. addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
  300. #else
  301. swi r1, r0, TOPHYS(pt_pool_space + PT_R1); /* GET_SP */
  302. /* Save date to kernel memory. Here is the problem
  303. * when you came from user space */
  304. ori r1, r0, TOPHYS(pt_pool_space);
  305. #endif
  306. swi r3, r1, PT_R3
  307. swi r4, r1, PT_R4
  308. swi r5, r1, PT_R5
  309. swi r6, r1, PT_R6
  310. #ifdef CONFIG_MMU
  311. swi r11, r1, PT_R11
  312. swi r31, r1, PT_R31
  313. lwi r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */
  314. #endif
  315. mfs r5, rmsr;
  316. nop
  317. swi r5, r1, 0;
  318. mfs r4, resr
  319. nop
  320. mfs r3, rear;
  321. nop
  322. #ifndef CONFIG_MMU
  323. andi r5, r4, 0x1000; /* Check ESR[DS] */
  324. beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
  325. mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
  326. nop
  327. not_in_delay_slot:
  328. swi r17, r1, PT_R17
  329. #endif
  330. andi r5, r4, 0x1F; /* Extract ESR[EXC] */
  331. #ifdef CONFIG_MMU
  332. /* Calculate exception vector offset = r5 << 2 */
  333. addk r6, r5, r5; /* << 1 */
  334. addk r6, r6, r6; /* << 2 */
  335. #ifdef DEBUG
  336. /* counting which exception happen */
  337. lwi r5, r0, TOPHYS(exception_debug_table)
  338. addi r5, r5, 1
  339. swi r5, r0, TOPHYS(exception_debug_table)
  340. lwi r5, r6, TOPHYS(exception_debug_table)
  341. addi r5, r5, 1
  342. swi r5, r6, TOPHYS(exception_debug_table)
  343. #endif
  344. /* end */
  345. /* Load the HW Exception vector */
  346. lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
  347. bra r6
  348. full_exception_trapw:
  349. RESTORE_STATE
  350. bri full_exception_trap
  351. #else
  352. /* Exceptions enabled here. This will allow nested exceptions */
  353. mfs r6, rmsr;
  354. nop
  355. swi r6, r1, 0; /* RMSR_OFFSET */
  356. ori r6, r6, 0x100; /* Turn ON the EE bit */
  357. andi r6, r6, ~2; /* Disable interrupts */
  358. mts rmsr, r6;
  359. nop
  360. xori r6, r5, 1; /* 00001 = Unaligned Exception */
  361. /* Jump to unalignment exception handler */
  362. beqi r6, handle_unaligned_ex;
  363. handle_other_ex: /* Handle Other exceptions here */
  364. /* Save other volatiles before we make procedure calls below */
  365. swi r7, r1, PT_R7
  366. swi r8, r1, PT_R8
  367. swi r9, r1, PT_R9
  368. swi r10, r1, PT_R10
  369. swi r11, r1, PT_R11
  370. swi r12, r1, PT_R12
  371. swi r14, r1, PT_R14
  372. swi r15, r1, PT_R15
  373. swi r18, r1, PT_R18
  374. or r5, r1, r0
  375. andi r6, r4, 0x1F; /* Load ESR[EC] */
  376. lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */
  377. swi r7, r1, PT_MODE
  378. mfs r7, rfsr
  379. nop
  380. addk r8, r17, r0; /* Load exception address */
  381. bralid r15, full_exception; /* Branch to the handler */
  382. nop;
  383. mts rfsr, r0; /* Clear sticky fsr */
  384. nop
  385. /*
  386. * Trigger execution of the signal handler by enabling
  387. * interrupts and calling an invalid syscall.
  388. */
  389. mfs r5, rmsr;
  390. nop
  391. ori r5, r5, 2;
  392. mts rmsr, r5; /* enable interrupt */
  393. nop
  394. addi r12, r0, __NR_syscalls;
  395. brki r14, 0x08;
  396. mfs r5, rmsr; /* disable interrupt */
  397. nop
  398. andi r5, r5, ~2;
  399. mts rmsr, r5;
  400. nop
  401. lwi r7, r1, PT_R7
  402. lwi r8, r1, PT_R8
  403. lwi r9, r1, PT_R9
  404. lwi r10, r1, PT_R10
  405. lwi r11, r1, PT_R11
  406. lwi r12, r1, PT_R12
  407. lwi r14, r1, PT_R14
  408. lwi r15, r1, PT_R15
  409. lwi r18, r1, PT_R18
  410. bri ex_handler_done; /* Complete exception handling */
  411. #endif
  412. /* 0x01 - Unaligned data access exception
  413. * This occurs when a word access is not aligned on a word boundary,
  414. * or when a 16-bit access is not aligned on a 16-bit boundary.
  415. * This handler perform the access, and returns, except for MMU when
  416. * the unaligned address is last on a 4k page or the physical address is
  417. * not found in the page table, in which case unaligned_data_trap is called.
  418. */
  419. handle_unaligned_ex:
  420. /* Working registers already saved: R3, R4, R5, R6
  421. * R4 = ESR
  422. * R3 = EAR
  423. */
  424. #ifdef CONFIG_MMU
  425. andi r6, r4, 0x1000 /* Check ESR[DS] */
  426. beqi r6, _no_delayslot /* Branch if ESR[DS] not set */
  427. mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
  428. nop
  429. _no_delayslot:
  430. /* jump to high level unaligned handler */
  431. RESTORE_STATE;
  432. bri unaligned_data_trap
  433. #endif
  434. andi r6, r4, 0x3E0; /* Mask and extract the register operand */
  435. srl r6, r6; /* r6 >> 5 */
  436. srl r6, r6;
  437. srl r6, r6;
  438. srl r6, r6;
  439. srl r6, r6;
  440. /* Store the register operand in a temporary location */
  441. sbi r6, r0, TOPHYS(ex_reg_op);
  442. andi r6, r4, 0x400; /* Extract ESR[S] */
  443. bnei r6, ex_sw;
  444. ex_lw:
  445. andi r6, r4, 0x800; /* Extract ESR[W] */
  446. beqi r6, ex_lhw;
  447. lbui r5, r3, 0; /* Exception address in r3 */
  448. /* Load a word, byte-by-byte from destination address
  449. and save it in tmp space */
  450. sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
  451. lbui r5, r3, 1;
  452. sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
  453. lbui r5, r3, 2;
  454. sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);
  455. lbui r5, r3, 3;
  456. sbi r5, r0, TOPHYS(ex_tmp_data_loc_3);
  457. /* Get the destination register value into r4 */
  458. lwi r4, r0, TOPHYS(ex_tmp_data_loc_0);
  459. bri ex_lw_tail;
  460. ex_lhw:
  461. lbui r5, r3, 0; /* Exception address in r3 */
  462. /* Load a half-word, byte-by-byte from destination
  463. address and save it in tmp space */
  464. sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
  465. lbui r5, r3, 1;
  466. sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
  467. /* Get the destination register value into r4 */
  468. lhui r4, r0, TOPHYS(ex_tmp_data_loc_0);
  469. ex_lw_tail:
  470. /* Get the destination register number into r5 */
  471. lbui r5, r0, TOPHYS(ex_reg_op);
  472. /* Form load_word jump table offset (lw_table + (8 * regnum)) */
  473. addik r6, r0, TOPHYS(lw_table);
  474. addk r5, r5, r5;
  475. addk r5, r5, r5;
  476. addk r5, r5, r5;
  477. addk r5, r5, r6;
  478. bra r5;
  479. ex_lw_end: /* Exception handling of load word, ends */
  480. ex_sw:
  481. /* Get the destination register number into r5 */
  482. lbui r5, r0, TOPHYS(ex_reg_op);
  483. /* Form store_word jump table offset (sw_table + (8 * regnum)) */
  484. addik r6, r0, TOPHYS(sw_table);
  485. add r5, r5, r5;
  486. add r5, r5, r5;
  487. add r5, r5, r5;
  488. add r5, r5, r6;
  489. bra r5;
  490. ex_sw_tail:
  491. mfs r6, resr;
  492. nop
  493. andi r6, r6, 0x800; /* Extract ESR[W] */
  494. beqi r6, ex_shw;
  495. /* Get the word - delay slot */
  496. swi r4, r0, TOPHYS(ex_tmp_data_loc_0);
  497. /* Store the word, byte-by-byte into destination address */
  498. lbui r4, r0, TOPHYS(ex_tmp_data_loc_0);
  499. sbi r4, r3, 0;
  500. lbui r4, r0, TOPHYS(ex_tmp_data_loc_1);
  501. sbi r4, r3, 1;
  502. lbui r4, r0, TOPHYS(ex_tmp_data_loc_2);
  503. sbi r4, r3, 2;
  504. lbui r4, r0, TOPHYS(ex_tmp_data_loc_3);
  505. sbi r4, r3, 3;
  506. bri ex_handler_done;
  507. ex_shw:
  508. /* Store the lower half-word, byte-by-byte into destination address */
  509. swi r4, r0, TOPHYS(ex_tmp_data_loc_0);
  510. lbui r4, r0, TOPHYS(ex_tmp_data_loc_2);
  511. sbi r4, r3, 0;
  512. lbui r4, r0, TOPHYS(ex_tmp_data_loc_3);
  513. sbi r4, r3, 1;
  514. ex_sw_end: /* Exception handling of store word, ends. */
  515. ex_handler_done:
  516. #ifndef CONFIG_MMU
  517. lwi r5, r1, 0 /* RMSR */
  518. mts rmsr, r5
  519. nop
  520. lwi r3, r1, PT_R3
  521. lwi r4, r1, PT_R4
  522. lwi r5, r1, PT_R5
  523. lwi r6, r1, PT_R6
  524. lwi r17, r1, PT_R17
  525. rted r17, 0
  526. addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
  527. #else
  528. RESTORE_STATE;
  529. rted r17, 0
  530. nop
  531. #endif
  532. #ifdef CONFIG_MMU
  533. /* Exception vector entry code. This code runs with address translation
  534. * turned off (i.e. using physical addresses). */
  535. /* Exception vectors. */
  536. /* 0x10 - Data Storage Exception
  537. * This happens for just a few reasons. U0 set (but we don't do that),
  538. * or zone protection fault (user violation, write to protected page).
  539. * If this is just an update of modified status, we do that quickly
  540. * and exit. Otherwise, we call heavyweight functions to do the work.
  541. */
  542. handle_data_storage_exception:
  543. /* Working registers already saved: R3, R4, R5, R6
  544. * R3 = ESR
  545. */
  546. mfs r11, rpid
  547. nop
  548. /* If we are faulting a kernel address, we have to use the
  549. * kernel page tables.
  550. */
  551. ori r5, r0, CONFIG_KERNEL_START
  552. cmpu r5, r3, r5
  553. bgti r5, ex3
  554. /* First, check if it was a zone fault (which means a user
  555. * tried to access a kernel or read-protected page - always
  556. * a SEGV). All other faults here must be stores, so no
  557. * need to check ESR_S as well. */
  558. andi r4, r4, ESR_DIZ /* ESR_Z - zone protection */
  559. bnei r4, ex2
  560. ori r4, r0, swapper_pg_dir
  561. mts rpid, r0 /* TLB will have 0 TID */
  562. nop
  563. bri ex4
  564. /* Get the PGD for the current thread. */
  565. ex3:
  566. /* First, check if it was a zone fault (which means a user
  567. * tried to access a kernel or read-protected page - always
  568. * a SEGV). All other faults here must be stores, so no
  569. * need to check ESR_S as well. */
  570. andi r4, r4, ESR_DIZ /* ESR_Z */
  571. bnei r4, ex2
  572. /* get current task address */
  573. addi r4 ,CURRENT_TASK, TOPHYS(0);
  574. lwi r4, r4, TASK_THREAD+PGDIR
  575. ex4:
  576. tophys(r4,r4)
  577. /* Create L1 (pgdir/pmd) address */
  578. bsrli r5, r3, PGDIR_SHIFT - 2
  579. andi r5, r5, PAGE_SIZE - 4
  580. /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
  581. or r4, r4, r5
  582. lwi r4, r4, 0 /* Get L1 entry */
  583. andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
  584. beqi r5, ex2 /* Bail if no table */
  585. tophys(r5,r5)
  586. bsrli r6, r3, PTE_SHIFT /* Compute PTE address */
  587. andi r6, r6, PAGE_SIZE - 4
  588. or r5, r5, r6
  589. lwi r4, r5, 0 /* Get Linux PTE */
  590. andi r6, r4, _PAGE_RW /* Is it writeable? */
  591. beqi r6, ex2 /* Bail if not */
  592. /* Update 'changed' */
  593. ori r4, r4, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
  594. swi r4, r5, 0 /* Update Linux page table */
  595. /* Most of the Linux PTE is ready to load into the TLB LO.
  596. * We set ZSEL, where only the LS-bit determines user access.
  597. * We set execute, because we don't have the granularity to
  598. * properly set this at the page level (Linux problem).
  599. * If shared is set, we cause a zero PID->TID load.
  600. * Many of these bits are software only. Bits we don't set
  601. * here we (properly should) assume have the appropriate value.
  602. */
  603. /* Ignore memory coherent, just LSB on ZSEL is used + EX/WR */
  604. andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
  605. TLB_ZSEL(1) | TLB_ATTR_MASK
  606. ori r4, r4, _PAGE_HWEXEC /* make it executable */
  607. /* find the TLB index that caused the fault. It has to be here*/
  608. mts rtlbsx, r3
  609. nop
  610. mfs r5, rtlbx /* DEBUG: TBD */
  611. nop
  612. mts rtlblo, r4 /* Load TLB LO */
  613. nop
  614. /* Will sync shadow TLBs */
  615. /* Done...restore registers and get out of here. */
  616. mts rpid, r11
  617. nop
  618. bri 4
  619. RESTORE_STATE;
  620. rted r17, 0
  621. nop
  622. ex2:
  623. /* The bailout. Restore registers to pre-exception conditions
  624. * and call the heavyweights to help us out. */
  625. mts rpid, r11
  626. nop
  627. bri 4
  628. RESTORE_STATE;
  629. bri page_fault_data_trap
  630. /* 0x11 - Instruction Storage Exception
  631. * This is caused by a fetch from non-execute or guarded pages. */
  632. handle_instruction_storage_exception:
  633. /* Working registers already saved: R3, R4, R5, R6
  634. * R3 = ESR
  635. */
  636. RESTORE_STATE;
  637. bri page_fault_instr_trap
  638. /* 0x12 - Data TLB Miss Exception
  639. * As the name implies, translation is not in the MMU, so search the
  640. * page tables and fix it. The only purpose of this function is to
  641. * load TLB entries from the page table if they exist.
  642. */
  643. handle_data_tlb_miss_exception:
  644. /* Working registers already saved: R3, R4, R5, R6
  645. * R3 = EAR, R4 = ESR
  646. */
  647. mfs r11, rpid
  648. nop
  649. /* If we are faulting a kernel address, we have to use the
  650. * kernel page tables. */
  651. ori r6, r0, CONFIG_KERNEL_START
  652. cmpu r4, r3, r6
  653. bgti r4, ex5
  654. ori r4, r0, swapper_pg_dir
  655. mts rpid, r0 /* TLB will have 0 TID */
  656. nop
  657. bri ex6
  658. /* Get the PGD for the current thread. */
  659. ex5:
  660. /* get current task address */
  661. addi r4 ,CURRENT_TASK, TOPHYS(0);
  662. lwi r4, r4, TASK_THREAD+PGDIR
  663. ex6:
  664. tophys(r4,r4)
  665. /* Create L1 (pgdir/pmd) address */
  666. bsrli r5, r3, PGDIR_SHIFT - 2
  667. andi r5, r5, PAGE_SIZE - 4
  668. /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
  669. or r4, r4, r5
  670. lwi r4, r4, 0 /* Get L1 entry */
  671. andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
  672. beqi r5, ex7 /* Bail if no table */
  673. tophys(r5,r5)
  674. bsrli r6, r3, PTE_SHIFT /* Compute PTE address */
  675. andi r6, r6, PAGE_SIZE - 4
  676. or r5, r5, r6
  677. lwi r4, r5, 0 /* Get Linux PTE */
  678. andi r6, r4, _PAGE_PRESENT
  679. beqi r6, ex7
  680. ori r4, r4, _PAGE_ACCESSED
  681. swi r4, r5, 0
  682. /* Most of the Linux PTE is ready to load into the TLB LO.
  683. * We set ZSEL, where only the LS-bit determines user access.
  684. * We set execute, because we don't have the granularity to
  685. * properly set this at the page level (Linux problem).
  686. * If shared is set, we cause a zero PID->TID load.
  687. * Many of these bits are software only. Bits we don't set
  688. * here we (properly should) assume have the appropriate value.
  689. */
  690. brid finish_tlb_load
  691. andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
  692. TLB_ZSEL(1) | TLB_ATTR_MASK
  693. ex7:
  694. /* The bailout. Restore registers to pre-exception conditions
  695. * and call the heavyweights to help us out.
  696. */
  697. mts rpid, r11
  698. nop
  699. bri 4
  700. RESTORE_STATE;
  701. bri page_fault_data_trap
  702. /* 0x13 - Instruction TLB Miss Exception
  703. * Nearly the same as above, except we get our information from
  704. * different registers and bailout to a different point.
  705. */
  706. handle_instruction_tlb_miss_exception:
  707. /* Working registers already saved: R3, R4, R5, R6
  708. * R3 = ESR
  709. */
  710. mfs r11, rpid
  711. nop
  712. /* If we are faulting a kernel address, we have to use the
  713. * kernel page tables.
  714. */
  715. ori r4, r0, CONFIG_KERNEL_START
  716. cmpu r4, r3, r4
  717. bgti r4, ex8
  718. ori r4, r0, swapper_pg_dir
  719. mts rpid, r0 /* TLB will have 0 TID */
  720. nop
  721. bri ex9
  722. /* Get the PGD for the current thread. */
  723. ex8:
  724. /* get current task address */
  725. addi r4 ,CURRENT_TASK, TOPHYS(0);
  726. lwi r4, r4, TASK_THREAD+PGDIR
  727. ex9:
  728. tophys(r4,r4)
  729. /* Create L1 (pgdir/pmd) address */
  730. bsrli r5, r3, PGDIR_SHIFT - 2
  731. andi r5, r5, PAGE_SIZE - 4
  732. /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
  733. or r4, r4, r5
  734. lwi r4, r4, 0 /* Get L1 entry */
  735. andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
  736. beqi r5, ex10 /* Bail if no table */
  737. tophys(r5,r5)
  738. bsrli r6, r3, PTE_SHIFT /* Compute PTE address */
  739. andi r6, r6, PAGE_SIZE - 4
  740. or r5, r5, r6
  741. lwi r4, r5, 0 /* Get Linux PTE */
  742. andi r6, r4, _PAGE_PRESENT
  743. beqi r6, ex10
  744. ori r4, r4, _PAGE_ACCESSED
  745. swi r4, r5, 0
  746. /* Most of the Linux PTE is ready to load into the TLB LO.
  747. * We set ZSEL, where only the LS-bit determines user access.
  748. * We set execute, because we don't have the granularity to
  749. * properly set this at the page level (Linux problem).
  750. * If shared is set, we cause a zero PID->TID load.
  751. * Many of these bits are software only. Bits we don't set
  752. * here we (properly should) assume have the appropriate value.
  753. */
  754. brid finish_tlb_load
  755. andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
  756. TLB_ZSEL(1) | TLB_ATTR_MASK
  757. ex10:
  758. /* The bailout. Restore registers to pre-exception conditions
  759. * and call the heavyweights to help us out.
  760. */
  761. mts rpid, r11
  762. nop
  763. bri 4
  764. RESTORE_STATE;
  765. bri page_fault_instr_trap
  766. /* Both the instruction and data TLB miss get to this point to load the TLB.
  767. * r3 - EA of fault
  768. * r4 - TLB LO (info from Linux PTE)
  769. * r5, r6 - available to use
  770. * PID - loaded with proper value when we get here
  771. * Upon exit, we reload everything and RFI.
  772. * A common place to load the TLB.
  773. */
  774. .section .data
  775. .align 4
  776. .global tlb_skip
  777. tlb_skip:
  778. .long MICROBLAZE_TLB_SKIP
  779. tlb_index:
  780. /* MS: storing last used tlb index */
  781. .long MICROBLAZE_TLB_SIZE/2
  782. .previous
  783. finish_tlb_load:
  784. /* MS: load the last used TLB index. */
  785. lwi r5, r0, TOPHYS(tlb_index)
  786. addik r5, r5, 1 /* MS: inc tlb_index -> use next one */
  787. /* MS: FIXME this is potential fault, because this is mask not count */
  788. andi r5, r5, MICROBLAZE_TLB_SIZE - 1
  789. ori r6, r0, 1
  790. cmp r31, r5, r6
  791. blti r31, ex12
  792. lwi r5, r0, TOPHYS(tlb_skip)
  793. ex12:
  794. /* MS: save back current TLB index */
  795. swi r5, r0, TOPHYS(tlb_index)
  796. ori r4, r4, _PAGE_HWEXEC /* make it executable */
  797. mts rtlbx, r5 /* MS: save current TLB */
  798. nop
  799. mts rtlblo, r4 /* MS: save to TLB LO */
  800. nop
  801. /* Create EPN. This is the faulting address plus a static
  802. * set of bits. These are size, valid, E, U0, and ensure
  803. * bits 20 and 21 are zero.
  804. */
  805. andi r3, r3, PAGE_MASK
  806. #ifdef CONFIG_MICROBLAZE_64K_PAGES
  807. ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_64K)
  808. #elif CONFIG_MICROBLAZE_16K_PAGES
  809. ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_16K)
  810. #else
  811. ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_4K)
  812. #endif
  813. mts rtlbhi, r3 /* Load TLB HI */
  814. nop
  815. /* Done...restore registers and get out of here. */
  816. mts rpid, r11
  817. nop
  818. bri 4
  819. RESTORE_STATE;
  820. rted r17, 0
  821. nop
  822. /* extern void giveup_fpu(struct task_struct *prev)
  823. *
  824. * The MicroBlaze processor may have an FPU, so this should not just
  825. * return: TBD.
  826. */
  827. .globl giveup_fpu;
  828. .align 4;
  829. giveup_fpu:
  830. bralid r15,0 /* TBD */
  831. nop
  832. /* At present, this routine just hangs. - extern void abort(void) */
  833. .globl abort;
  834. .align 4;
  835. abort:
  836. br r0
  837. .globl set_context;
  838. .align 4;
  839. set_context:
  840. mts rpid, r5 /* Shadow TLBs are automatically */
  841. nop
  842. bri 4 /* flushed by changing PID */
  843. rtsd r15,8
  844. nop
  845. #endif
  846. .end _hw_exception_handler
  847. #ifdef CONFIG_MMU
  848. /* Unaligned data access exception last on a 4k page for MMU.
  849. * When this is called, we are in virtual mode with exceptions enabled
  850. * and registers 1-13,15,17,18 saved.
  851. *
  852. * R3 = ESR
  853. * R4 = EAR
  854. * R7 = pointer to saved registers (struct pt_regs *regs)
  855. *
  856. * This handler perform the access, and returns via ret_from_exc.
  857. */
  858. .global _unaligned_data_exception
  859. .ent _unaligned_data_exception
  860. _unaligned_data_exception:
  861. andi r8, r3, 0x3E0; /* Mask and extract the register operand */
  862. bsrli r8, r8, 2; /* r8 >> 2 = register operand * 8 */
  863. andi r6, r3, 0x400; /* Extract ESR[S] */
  864. bneid r6, ex_sw_vm;
  865. andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */
  866. ex_lw_vm:
  867. beqid r6, ex_lhw_vm;
  868. load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
  869. /* Load a word, byte-by-byte from destination address and save it in tmp space*/
  870. addik r6, r0, ex_tmp_data_loc_0;
  871. sbi r5, r6, 0;
  872. load2: lbui r5, r4, 1;
  873. sbi r5, r6, 1;
  874. load3: lbui r5, r4, 2;
  875. sbi r5, r6, 2;
  876. load4: lbui r5, r4, 3;
  877. sbi r5, r6, 3;
  878. brid ex_lw_tail_vm;
  879. /* Get the destination register value into r3 - delay slot */
  880. lwi r3, r6, 0;
  881. ex_lhw_vm:
  882. /* Load a half-word, byte-by-byte from destination address and
  883. * save it in tmp space */
  884. addik r6, r0, ex_tmp_data_loc_0;
  885. sbi r5, r6, 0;
  886. load5: lbui r5, r4, 1;
  887. sbi r5, r6, 1;
  888. lhui r3, r6, 0; /* Get the destination register value into r3 */
  889. ex_lw_tail_vm:
  890. /* Form load_word jump table offset (lw_table_vm + (8 * regnum)) */
  891. addik r5, r8, lw_table_vm;
  892. bra r5;
  893. ex_lw_end_vm: /* Exception handling of load word, ends */
  894. brai ret_from_exc;
  895. ex_sw_vm:
  896. /* Form store_word jump table offset (sw_table_vm + (8 * regnum)) */
  897. addik r5, r8, sw_table_vm;
  898. bra r5;
  899. ex_sw_tail_vm:
  900. addik r5, r0, ex_tmp_data_loc_0;
  901. beqid r6, ex_shw_vm;
  902. swi r3, r5, 0; /* Get the word - delay slot */
  903. /* Store the word, byte-by-byte into destination address */
  904. lbui r3, r5, 0;
  905. store1: sbi r3, r4, 0;
  906. lbui r3, r5, 1;
  907. store2: sbi r3, r4, 1;
  908. lbui r3, r5, 2;
  909. store3: sbi r3, r4, 2;
  910. lbui r3, r5, 3;
  911. brid ret_from_exc;
  912. store4: sbi r3, r4, 3; /* Delay slot */
  913. ex_shw_vm:
  914. /* Store the lower half-word, byte-by-byte into destination address */
  915. #ifdef __MICROBLAZEEL__
  916. lbui r3, r5, 0;
  917. store5: sbi r3, r4, 0;
  918. lbui r3, r5, 1;
  919. brid ret_from_exc;
  920. store6: sbi r3, r4, 1; /* Delay slot */
  921. #else
  922. lbui r3, r5, 2;
  923. store5: sbi r3, r4, 0;
  924. lbui r3, r5, 3;
  925. brid ret_from_exc;
  926. store6: sbi r3, r4, 1; /* Delay slot */
  927. #endif
  928. ex_sw_end_vm: /* Exception handling of store word, ends. */
  929. /* We have to prevent cases that get/put_user macros get unaligned pointer
  930. * to bad page area. We have to find out which origin instruction caused it
  931. * and called fixup for that origin instruction not instruction in unaligned
  932. * handler */
  933. ex_unaligned_fixup:
  934. ori r5, r7, 0 /* setup pointer to pt_regs */
  935. lwi r6, r7, PT_PC; /* faulting address is one instruction above */
  936. addik r6, r6, -4 /* for finding proper fixup */
  937. swi r6, r7, PT_PC; /* a save back it to PT_PC */
  938. addik r7, r0, SIGSEGV
  939. /* call bad_page_fault for finding aligned fixup, fixup address is saved
  940. * in PT_PC which is used as return address from exception */
  941. addik r15, r0, ret_from_exc-8 /* setup return address */
  942. brid bad_page_fault
  943. nop
  944. /* We prevent all load/store because it could failed any attempt to access */
  945. .section __ex_table,"a";
  946. .word load1,ex_unaligned_fixup;
  947. .word load2,ex_unaligned_fixup;
  948. .word load3,ex_unaligned_fixup;
  949. .word load4,ex_unaligned_fixup;
  950. .word load5,ex_unaligned_fixup;
  951. .word store1,ex_unaligned_fixup;
  952. .word store2,ex_unaligned_fixup;
  953. .word store3,ex_unaligned_fixup;
  954. .word store4,ex_unaligned_fixup;
  955. .word store5,ex_unaligned_fixup;
  956. .word store6,ex_unaligned_fixup;
  957. .previous;
  958. .end _unaligned_data_exception
  959. #endif /* CONFIG_MMU */
  960. .global ex_handler_unhandled
  961. ex_handler_unhandled:
  962. /* FIXME add handle function for unhandled exception - dump register */
  963. bri 0
  964. /*
  965. * hw_exception_handler Jump Table
  966. * - Contains code snippets for each register that caused the unalign exception
  967. * - Hence exception handler is NOT self-modifying
  968. * - Separate table for load exceptions and store exceptions.
  969. * - Each table is of size: (8 * 32) = 256 bytes
  970. */
  971. .section .text
  972. .align 4
  973. lw_table:
  974. lw_r0: R3_TO_LWREG (0);
  975. lw_r1: LWREG_NOP;
  976. lw_r2: R3_TO_LWREG (2);
  977. lw_r3: R3_TO_LWREG_V (3);
  978. lw_r4: R3_TO_LWREG_V (4);
  979. lw_r5: R3_TO_LWREG_V (5);
  980. lw_r6: R3_TO_LWREG_V (6);
  981. lw_r7: R3_TO_LWREG (7);
  982. lw_r8: R3_TO_LWREG (8);
  983. lw_r9: R3_TO_LWREG (9);
  984. lw_r10: R3_TO_LWREG (10);
  985. lw_r11: R3_TO_LWREG (11);
  986. lw_r12: R3_TO_LWREG (12);
  987. lw_r13: R3_TO_LWREG (13);
  988. lw_r14: R3_TO_LWREG (14);
  989. lw_r15: R3_TO_LWREG (15);
  990. lw_r16: R3_TO_LWREG (16);
  991. lw_r17: LWREG_NOP;
  992. lw_r18: R3_TO_LWREG (18);
  993. lw_r19: R3_TO_LWREG (19);
  994. lw_r20: R3_TO_LWREG (20);
  995. lw_r21: R3_TO_LWREG (21);
  996. lw_r22: R3_TO_LWREG (22);
  997. lw_r23: R3_TO_LWREG (23);
  998. lw_r24: R3_TO_LWREG (24);
  999. lw_r25: R3_TO_LWREG (25);
  1000. lw_r26: R3_TO_LWREG (26);
  1001. lw_r27: R3_TO_LWREG (27);
  1002. lw_r28: R3_TO_LWREG (28);
  1003. lw_r29: R3_TO_LWREG (29);
  1004. lw_r30: R3_TO_LWREG (30);
  1005. #ifdef CONFIG_MMU
  1006. lw_r31: R3_TO_LWREG_V (31);
  1007. #else
  1008. lw_r31: R3_TO_LWREG (31);
  1009. #endif
  1010. sw_table:
  1011. sw_r0: SWREG_TO_R3 (0);
  1012. sw_r1: SWREG_NOP;
  1013. sw_r2: SWREG_TO_R3 (2);
  1014. sw_r3: SWREG_TO_R3_V (3);
  1015. sw_r4: SWREG_TO_R3_V (4);
  1016. sw_r5: SWREG_TO_R3_V (5);
  1017. sw_r6: SWREG_TO_R3_V (6);
  1018. sw_r7: SWREG_TO_R3 (7);
  1019. sw_r8: SWREG_TO_R3 (8);
  1020. sw_r9: SWREG_TO_R3 (9);
  1021. sw_r10: SWREG_TO_R3 (10);
  1022. sw_r11: SWREG_TO_R3 (11);
  1023. sw_r12: SWREG_TO_R3 (12);
  1024. sw_r13: SWREG_TO_R3 (13);
  1025. sw_r14: SWREG_TO_R3 (14);
  1026. sw_r15: SWREG_TO_R3 (15);
  1027. sw_r16: SWREG_TO_R3 (16);
  1028. sw_r17: SWREG_NOP;
  1029. sw_r18: SWREG_TO_R3 (18);
  1030. sw_r19: SWREG_TO_R3 (19);
  1031. sw_r20: SWREG_TO_R3 (20);
  1032. sw_r21: SWREG_TO_R3 (21);
  1033. sw_r22: SWREG_TO_R3 (22);
  1034. sw_r23: SWREG_TO_R3 (23);
  1035. sw_r24: SWREG_TO_R3 (24);
  1036. sw_r25: SWREG_TO_R3 (25);
  1037. sw_r26: SWREG_TO_R3 (26);
  1038. sw_r27: SWREG_TO_R3 (27);
  1039. sw_r28: SWREG_TO_R3 (28);
  1040. sw_r29: SWREG_TO_R3 (29);
  1041. sw_r30: SWREG_TO_R3 (30);
  1042. #ifdef CONFIG_MMU
  1043. sw_r31: SWREG_TO_R3_V (31);
  1044. #else
  1045. sw_r31: SWREG_TO_R3 (31);
  1046. #endif
  1047. #ifdef CONFIG_MMU
  1048. lw_table_vm:
  1049. lw_r0_vm: R3_TO_LWREG_VM (0);
  1050. lw_r1_vm: R3_TO_LWREG_VM_V (1);
  1051. lw_r2_vm: R3_TO_LWREG_VM_V (2);
  1052. lw_r3_vm: R3_TO_LWREG_VM_V (3);
  1053. lw_r4_vm: R3_TO_LWREG_VM_V (4);
  1054. lw_r5_vm: R3_TO_LWREG_VM_V (5);
  1055. lw_r6_vm: R3_TO_LWREG_VM_V (6);
  1056. lw_r7_vm: R3_TO_LWREG_VM_V (7);
  1057. lw_r8_vm: R3_TO_LWREG_VM_V (8);
  1058. lw_r9_vm: R3_TO_LWREG_VM_V (9);
  1059. lw_r10_vm: R3_TO_LWREG_VM_V (10);
  1060. lw_r11_vm: R3_TO_LWREG_VM_V (11);
  1061. lw_r12_vm: R3_TO_LWREG_VM_V (12);
  1062. lw_r13_vm: R3_TO_LWREG_VM_V (13);
  1063. lw_r14_vm: R3_TO_LWREG_VM_V (14);
  1064. lw_r15_vm: R3_TO_LWREG_VM_V (15);
  1065. lw_r16_vm: R3_TO_LWREG_VM_V (16);
  1066. lw_r17_vm: R3_TO_LWREG_VM_V (17);
  1067. lw_r18_vm: R3_TO_LWREG_VM_V (18);
  1068. lw_r19_vm: R3_TO_LWREG_VM_V (19);
  1069. lw_r20_vm: R3_TO_LWREG_VM_V (20);
  1070. lw_r21_vm: R3_TO_LWREG_VM_V (21);
  1071. lw_r22_vm: R3_TO_LWREG_VM_V (22);
  1072. lw_r23_vm: R3_TO_LWREG_VM_V (23);
  1073. lw_r24_vm: R3_TO_LWREG_VM_V (24);
  1074. lw_r25_vm: R3_TO_LWREG_VM_V (25);
  1075. lw_r26_vm: R3_TO_LWREG_VM_V (26);
  1076. lw_r27_vm: R3_TO_LWREG_VM_V (27);
  1077. lw_r28_vm: R3_TO_LWREG_VM_V (28);
  1078. lw_r29_vm: R3_TO_LWREG_VM_V (29);
  1079. lw_r30_vm: R3_TO_LWREG_VM_V (30);
  1080. lw_r31_vm: R3_TO_LWREG_VM_V (31);
  1081. sw_table_vm:
  1082. sw_r0_vm: SWREG_TO_R3_VM (0);
  1083. sw_r1_vm: SWREG_TO_R3_VM_V (1);
  1084. sw_r2_vm: SWREG_TO_R3_VM_V (2);
  1085. sw_r3_vm: SWREG_TO_R3_VM_V (3);
  1086. sw_r4_vm: SWREG_TO_R3_VM_V (4);
  1087. sw_r5_vm: SWREG_TO_R3_VM_V (5);
  1088. sw_r6_vm: SWREG_TO_R3_VM_V (6);
  1089. sw_r7_vm: SWREG_TO_R3_VM_V (7);
  1090. sw_r8_vm: SWREG_TO_R3_VM_V (8);
  1091. sw_r9_vm: SWREG_TO_R3_VM_V (9);
  1092. sw_r10_vm: SWREG_TO_R3_VM_V (10);
  1093. sw_r11_vm: SWREG_TO_R3_VM_V (11);
  1094. sw_r12_vm: SWREG_TO_R3_VM_V (12);
  1095. sw_r13_vm: SWREG_TO_R3_VM_V (13);
  1096. sw_r14_vm: SWREG_TO_R3_VM_V (14);
  1097. sw_r15_vm: SWREG_TO_R3_VM_V (15);
  1098. sw_r16_vm: SWREG_TO_R3_VM_V (16);
  1099. sw_r17_vm: SWREG_TO_R3_VM_V (17);
  1100. sw_r18_vm: SWREG_TO_R3_VM_V (18);
  1101. sw_r19_vm: SWREG_TO_R3_VM_V (19);
  1102. sw_r20_vm: SWREG_TO_R3_VM_V (20);
  1103. sw_r21_vm: SWREG_TO_R3_VM_V (21);
  1104. sw_r22_vm: SWREG_TO_R3_VM_V (22);
  1105. sw_r23_vm: SWREG_TO_R3_VM_V (23);
  1106. sw_r24_vm: SWREG_TO_R3_VM_V (24);
  1107. sw_r25_vm: SWREG_TO_R3_VM_V (25);
  1108. sw_r26_vm: SWREG_TO_R3_VM_V (26);
  1109. sw_r27_vm: SWREG_TO_R3_VM_V (27);
  1110. sw_r28_vm: SWREG_TO_R3_VM_V (28);
  1111. sw_r29_vm: SWREG_TO_R3_VM_V (29);
  1112. sw_r30_vm: SWREG_TO_R3_VM_V (30);
  1113. sw_r31_vm: SWREG_TO_R3_VM_V (31);
  1114. #endif /* CONFIG_MMU */
  1115. /* Temporary data structures used in the handler */
  1116. .section .data
  1117. .align 4
  1118. ex_tmp_data_loc_0:
  1119. .byte 0
  1120. ex_tmp_data_loc_1:
  1121. .byte 0
  1122. ex_tmp_data_loc_2:
  1123. .byte 0
  1124. ex_tmp_data_loc_3:
  1125. .byte 0
  1126. ex_reg_op:
  1127. .byte 0