pcibios.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * pci.c -- basic PCI support code
  4. *
  5. * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/types.h>
  9. #include <linux/mm.h>
  10. #include <linux/init.h>
  11. #include <linux/pci.h>
  12. /*
  13. * From arch/i386/kernel/pci-i386.c:
  14. *
  15. * We need to avoid collisions with `mirrored' VGA ports
  16. * and other strange ISA hardware, so we always want the
  17. * addresses to be allocated in the 0x000-0x0ff region
  18. * modulo 0x400.
  19. *
  20. * Why? Because some silly external IO cards only decode
  21. * the low 10 bits of the IO address. The 0x00-0xff region
  22. * is reserved for motherboard devices that decode all 16
  23. * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  24. * but we want to try to avoid allocating at 0x2900-0x2bff
  25. * which might be mirrored at 0x0100-0x03ff..
  26. */
  27. resource_size_t pcibios_align_resource(void *data, const struct resource *res,
  28. resource_size_t size, resource_size_t align)
  29. {
  30. resource_size_t start = res->start;
  31. if ((res->flags & IORESOURCE_IO) && (start & 0x300))
  32. start = (start + 0x3ff) & ~0x3ff;
  33. start = (start + align - 1) & ~(align - 1);
  34. return start;
  35. }
  36. /*
  37. * This is taken from the ARM code for this.
  38. */
  39. int pcibios_enable_device(struct pci_dev *dev, int mask)
  40. {
  41. struct resource *r;
  42. u16 cmd, newcmd;
  43. int idx;
  44. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  45. newcmd = cmd;
  46. for (idx = 0; idx < 6; idx++) {
  47. /* Only set up the requested stuff */
  48. if (!(mask & (1 << idx)))
  49. continue;
  50. r = dev->resource + idx;
  51. if (!r->start && r->end) {
  52. pr_err("PCI: Device %s not available because of resource collisions\n",
  53. pci_name(dev));
  54. return -EINVAL;
  55. }
  56. if (r->flags & IORESOURCE_IO)
  57. newcmd |= PCI_COMMAND_IO;
  58. if (r->flags & IORESOURCE_MEM)
  59. newcmd |= PCI_COMMAND_MEMORY;
  60. }
  61. /*
  62. * Bridges (eg, cardbus bridges) need to be fully enabled
  63. */
  64. if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
  65. newcmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  66. if (newcmd != cmd) {
  67. pr_info("PCI: enabling device %s (0x%04x -> 0x%04x)\n",
  68. pci_name(dev), cmd, newcmd);
  69. pci_write_config_word(dev, PCI_COMMAND, newcmd);
  70. }
  71. return 0;
  72. }
  73. void pcibios_fixup_bus(struct pci_bus *bus)
  74. {
  75. struct pci_dev *dev;
  76. list_for_each_entry(dev, &bus->devices, bus_list) {
  77. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
  78. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 32);
  79. }
  80. }
  81. char *pcibios_setup(char *str)
  82. {
  83. return str;
  84. }