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  1. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  2. MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
  3. M68000 Hi-Performance Microprocessor Division
  4. M68060 Software Package
  5. Production Release P1.00 -- October 10, 1994
  6. M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
  7. THE SOFTWARE is provided on an "AS IS" basis and without warranty.
  8. To the maximum extent permitted by applicable law,
  9. MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
  10. INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
  11. and any warranty against infringement with regard to the SOFTWARE
  12. (INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
  13. To the maximum extent permitted by applicable law,
  14. IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
  15. (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
  16. BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
  17. ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
  18. Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
  19. You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
  20. so long as this entire notice is retained without alteration in any modified and/or
  21. redistributed versions, and that such modified versions are clearly identified as such.
  22. No licenses are granted by implication, estoppel or otherwise under any patents
  23. or trademarks of Motorola, Inc.
  24. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  25. CHANGES SINCE LAST RELEASE:
  26. ---------------------------
  27. 1) "movep" emulation where data was being read from memory
  28. was reading the intermediate bytes. Emulation now only
  29. reads the required bytes.
  30. 2) "flogn", "flog2", and "flog10" of "1" was setting the
  31. Inexact FPSR bit. Emulation now does not set Inexact for
  32. this case.
  33. 3) For an opclass three FP instruction where the effective addressing
  34. mode was pre-decrement or post-increment and the address register
  35. was A0 or A1, the address register was not being updated as a result
  36. of the operation. This has been corrected.
  37. 4) Beta B.2 version had the following erratum:
  38. Scenario:
  39. ---------
  40. If {i,d}mem_{read,write}_{byte,word,long}() returns
  41. a failing value to the 68060SP, the package ignores
  42. this return value and continues with program execution
  43. as if it never received a failing value.
  44. Effect:
  45. -------
  46. For example, if a user executed "fsin.x ADDR,fp0" where
  47. ADDR should cause a "segmentation violation", the memory read
  48. requested by the package should return a failing value
  49. to the package. Since the package currently ignores this
  50. return value, the user program will continue to the
  51. next instruction, and the result created in fp0 will be
  52. undefined.
  53. Fix:
  54. ----
  55. This has been fixed in the current release.
  56. Notes:
  57. ------
  58. Upon receiving a non-zero (failing) return value from
  59. a {i,d}mem_{read,write}_{byte,word,long}() "call-out",
  60. the package creates a 16-byte access error stack frame
  61. from the current exception stack frame and exits
  62. through the "call-out" _real_access(). This is the process
  63. as described in the MC68060 User's Manual.
  64. For instruction read access errors, the info stacked is:
  65. SR = SR at time of exception
  66. PC = PC of instruction being emulated
  67. VOFF = $4008 (stack frame format type)
  68. ADDRESS = PC of instruction being emulated
  69. FSLW = FAULT STATUS LONGWORD
  70. The valid FSLW bits are:
  71. bit 27 = 1 (misaligned bit)
  72. bit 24 = 1 (read)
  73. bit 23 = 0 (write)
  74. bit 22:21 = 10 (SIZE = word)
  75. bit 20:19 = 00 (TT)
  76. bit 18:16 = x10 (TM; x = 1 for supervisor mode)
  77. bit 15 = 1 (IO)
  78. bit 0 = 1 (Software Emulation Error)
  79. all other bits are EQUAL TO ZERO and can be set by the _real_access()
  80. "call-out" stub by the user as appropriate. The MC68060 User's Manual
  81. stated that ONLY "bit 0" would be set. The 060SP attempts to set a few
  82. other bits.
  83. For data read/write access errors, the info stacked is:
  84. SR = SR at time of exception
  85. PC = PC of instruction being emulated
  86. VOFF = $4008 (stack frame format type)
  87. ADDRESS = Address of source or destination operand
  88. FSLW = FAULT STATUS LONGWORD
  89. The valid FSLW bits are:
  90. bit 27 = 0 (misaligned bit)
  91. bit 24 = x (read; 1 if read, 0 if write)
  92. bit 23 = x (write; 1 if write, 0 if read)
  93. bit 22:21 = xx (SIZE; see MC68060 User's Manual)
  94. bit 20:19 = 00 (TT)
  95. bit 18:16 = x01 (TM; x = 1 for supervisor mode)
  96. bit 15 = 0 (IO)
  97. bit 0 = 1 (Software Emulation Error)
  98. all other bits are EQUAL TO ZERO and can be set by the _real_access()
  99. "call-out" stub by the user as appropriate. The MC68060 User's Manual
  100. stated that ONLY "bit 0" would be set. The 060SP attempts to set a few
  101. other bits.