irq_cpu.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * First-level interrupt controller model for Hexagon.
  4. *
  5. * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
  6. */
  7. #include <linux/interrupt.h>
  8. #include <asm/irq.h>
  9. #include <asm/hexagon_vm.h>
  10. static void mask_irq(struct irq_data *data)
  11. {
  12. __vmintop_locdis((long) data->irq);
  13. }
  14. static void mask_irq_num(unsigned int irq)
  15. {
  16. __vmintop_locdis((long) irq);
  17. }
  18. static void unmask_irq(struct irq_data *data)
  19. {
  20. __vmintop_locen((long) data->irq);
  21. }
  22. /* This is actually all we need for handle_fasteoi_irq */
  23. static void eoi_irq(struct irq_data *data)
  24. {
  25. __vmintop_globen((long) data->irq);
  26. }
  27. /* Power mamangement wake call. We don't need this, however,
  28. * if this is absent, then an -ENXIO error is returned to the
  29. * msm_serial driver, and it fails to correctly initialize.
  30. * This is a bug in the msm_serial driver, but, for now, we
  31. * work around it here, by providing this bogus handler.
  32. * XXX FIXME!!! remove this when msm_serial is fixed.
  33. */
  34. static int set_wake(struct irq_data *data, unsigned int on)
  35. {
  36. return 0;
  37. }
  38. static struct irq_chip hexagon_irq_chip = {
  39. .name = "HEXAGON",
  40. .irq_mask = mask_irq,
  41. .irq_unmask = unmask_irq,
  42. .irq_set_wake = set_wake,
  43. .irq_eoi = eoi_irq
  44. };
  45. /**
  46. * The hexagon core comes with a first-level interrupt controller
  47. * with 32 total possible interrupts. When the core is embedded
  48. * into different systems/platforms, it is typically wrapped by
  49. * macro cells that provide one or more second-level interrupt
  50. * controllers that are cascaded into one or more of the first-level
  51. * interrupts handled here. The precise wiring of these other
  52. * irqs varies from platform to platform, and are set up & configured
  53. * in the platform-specific files.
  54. *
  55. * The first-level interrupt controller is wrapped by the VM, which
  56. * virtualizes the interrupt controller for us. It provides a very
  57. * simple, fast & efficient API, and so the fasteoi handler is
  58. * appropriate for this case.
  59. */
  60. void __init init_IRQ(void)
  61. {
  62. int irq;
  63. for (irq = 0; irq < HEXAGON_CPUINTS; irq++) {
  64. mask_irq_num(irq);
  65. irq_set_chip_and_handler(irq, &hexagon_irq_chip,
  66. handle_fasteoi_irq);
  67. }
  68. }