megamod-pic.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Support for C64x+ Megamodule Interrupt Controller
  4. *
  5. * Copyright (C) 2010, 2011 Texas Instruments Incorporated
  6. * Contributed by: Mark Salter <msalter@redhat.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/io.h>
  11. #include <linux/of.h>
  12. #include <linux/of_irq.h>
  13. #include <linux/of_address.h>
  14. #include <linux/slab.h>
  15. #include <asm/soc.h>
  16. #include <asm/megamod-pic.h>
  17. #define NR_COMBINERS 4
  18. #define NR_MUX_OUTPUTS 12
  19. #define IRQ_UNMAPPED 0xffff
  20. /*
  21. * Megamodule Interrupt Controller register layout
  22. */
  23. struct megamod_regs {
  24. u32 evtflag[8];
  25. u32 evtset[8];
  26. u32 evtclr[8];
  27. u32 reserved0[8];
  28. u32 evtmask[8];
  29. u32 mevtflag[8];
  30. u32 expmask[8];
  31. u32 mexpflag[8];
  32. u32 intmux_unused;
  33. u32 intmux[7];
  34. u32 reserved1[8];
  35. u32 aegmux[2];
  36. u32 reserved2[14];
  37. u32 intxstat;
  38. u32 intxclr;
  39. u32 intdmask;
  40. u32 reserved3[13];
  41. u32 evtasrt;
  42. };
  43. struct megamod_pic {
  44. struct irq_domain *irqhost;
  45. struct megamod_regs __iomem *regs;
  46. raw_spinlock_t lock;
  47. /* hw mux mapping */
  48. unsigned int output_to_irq[NR_MUX_OUTPUTS];
  49. };
  50. static struct megamod_pic *mm_pic;
  51. struct megamod_cascade_data {
  52. struct megamod_pic *pic;
  53. int index;
  54. };
  55. static struct megamod_cascade_data cascade_data[NR_COMBINERS];
  56. static void mask_megamod(struct irq_data *data)
  57. {
  58. struct megamod_pic *pic = irq_data_get_irq_chip_data(data);
  59. irq_hw_number_t src = irqd_to_hwirq(data);
  60. u32 __iomem *evtmask = &pic->regs->evtmask[src / 32];
  61. raw_spin_lock(&pic->lock);
  62. soc_writel(soc_readl(evtmask) | (1 << (src & 31)), evtmask);
  63. raw_spin_unlock(&pic->lock);
  64. }
  65. static void unmask_megamod(struct irq_data *data)
  66. {
  67. struct megamod_pic *pic = irq_data_get_irq_chip_data(data);
  68. irq_hw_number_t src = irqd_to_hwirq(data);
  69. u32 __iomem *evtmask = &pic->regs->evtmask[src / 32];
  70. raw_spin_lock(&pic->lock);
  71. soc_writel(soc_readl(evtmask) & ~(1 << (src & 31)), evtmask);
  72. raw_spin_unlock(&pic->lock);
  73. }
  74. static struct irq_chip megamod_chip = {
  75. .name = "megamod",
  76. .irq_mask = mask_megamod,
  77. .irq_unmask = unmask_megamod,
  78. };
  79. static void megamod_irq_cascade(struct irq_desc *desc)
  80. {
  81. struct megamod_cascade_data *cascade;
  82. struct megamod_pic *pic;
  83. unsigned int irq;
  84. u32 events;
  85. int n, idx;
  86. cascade = irq_desc_get_handler_data(desc);
  87. pic = cascade->pic;
  88. idx = cascade->index;
  89. while ((events = soc_readl(&pic->regs->mevtflag[idx])) != 0) {
  90. n = __ffs(events);
  91. irq = irq_linear_revmap(pic->irqhost, idx * 32 + n);
  92. soc_writel(1 << n, &pic->regs->evtclr[idx]);
  93. generic_handle_irq(irq);
  94. }
  95. }
  96. static int megamod_map(struct irq_domain *h, unsigned int virq,
  97. irq_hw_number_t hw)
  98. {
  99. struct megamod_pic *pic = h->host_data;
  100. int i;
  101. /* We shouldn't see a hwirq which is muxed to core controller */
  102. for (i = 0; i < NR_MUX_OUTPUTS; i++)
  103. if (pic->output_to_irq[i] == hw)
  104. return -1;
  105. irq_set_chip_data(virq, pic);
  106. irq_set_chip_and_handler(virq, &megamod_chip, handle_level_irq);
  107. /* Set default irq type */
  108. irq_set_irq_type(virq, IRQ_TYPE_NONE);
  109. return 0;
  110. }
  111. static const struct irq_domain_ops megamod_domain_ops = {
  112. .map = megamod_map,
  113. .xlate = irq_domain_xlate_onecell,
  114. };
  115. static void __init set_megamod_mux(struct megamod_pic *pic, int src, int output)
  116. {
  117. int index, offset;
  118. u32 val;
  119. if (src < 0 || src >= (NR_COMBINERS * 32)) {
  120. pic->output_to_irq[output] = IRQ_UNMAPPED;
  121. return;
  122. }
  123. /* four mappings per mux register */
  124. index = output / 4;
  125. offset = (output & 3) * 8;
  126. val = soc_readl(&pic->regs->intmux[index]);
  127. val &= ~(0xff << offset);
  128. val |= src << offset;
  129. soc_writel(val, &pic->regs->intmux[index]);
  130. }
  131. /*
  132. * Parse the MUX mapping, if one exists.
  133. *
  134. * The MUX map is an array of up to 12 cells; one for each usable core priority
  135. * interrupt. The value of a given cell is the megamodule interrupt source
  136. * which is to me MUXed to the output corresponding to the cell position
  137. * withing the array. The first cell in the array corresponds to priority
  138. * 4 and the last (12th) cell corresponds to priority 15. The allowed
  139. * values are 4 - ((NR_COMBINERS * 32) - 1). Note that the combined interrupt
  140. * sources (0 - 3) are not allowed to be mapped through this property. They
  141. * are handled through the "interrupts" property. This allows us to use a
  142. * value of zero as a "do not map" placeholder.
  143. */
  144. static void __init parse_priority_map(struct megamod_pic *pic,
  145. int *mapping, int size)
  146. {
  147. struct device_node *np = irq_domain_get_of_node(pic->irqhost);
  148. const __be32 *map;
  149. int i, maplen;
  150. u32 val;
  151. map = of_get_property(np, "ti,c64x+megamod-pic-mux", &maplen);
  152. if (map) {
  153. maplen /= 4;
  154. if (maplen > size)
  155. maplen = size;
  156. for (i = 0; i < maplen; i++) {
  157. val = be32_to_cpup(map);
  158. if (val && val >= 4)
  159. mapping[i] = val;
  160. ++map;
  161. }
  162. }
  163. }
  164. static struct megamod_pic * __init init_megamod_pic(struct device_node *np)
  165. {
  166. struct megamod_pic *pic;
  167. int i, irq;
  168. int mapping[NR_MUX_OUTPUTS];
  169. pr_info("Initializing C64x+ Megamodule PIC\n");
  170. pic = kzalloc(sizeof(struct megamod_pic), GFP_KERNEL);
  171. if (!pic) {
  172. pr_err("%pOF: Could not alloc PIC structure.\n", np);
  173. return NULL;
  174. }
  175. pic->irqhost = irq_domain_add_linear(np, NR_COMBINERS * 32,
  176. &megamod_domain_ops, pic);
  177. if (!pic->irqhost) {
  178. pr_err("%pOF: Could not alloc host.\n", np);
  179. goto error_free;
  180. }
  181. pic->irqhost->host_data = pic;
  182. raw_spin_lock_init(&pic->lock);
  183. pic->regs = of_iomap(np, 0);
  184. if (!pic->regs) {
  185. pr_err("%pOF: Could not map registers.\n", np);
  186. goto error_free;
  187. }
  188. /* Initialize MUX map */
  189. for (i = 0; i < ARRAY_SIZE(mapping); i++)
  190. mapping[i] = IRQ_UNMAPPED;
  191. parse_priority_map(pic, mapping, ARRAY_SIZE(mapping));
  192. /*
  193. * We can have up to 12 interrupts cascading to the core controller.
  194. * These cascades can be from the combined interrupt sources or for
  195. * individual interrupt sources. The "interrupts" property only
  196. * deals with the cascaded combined interrupts. The individual
  197. * interrupts muxed to the core controller use the core controller
  198. * as their interrupt parent.
  199. */
  200. for (i = 0; i < NR_COMBINERS; i++) {
  201. struct irq_data *irq_data;
  202. irq_hw_number_t hwirq;
  203. irq = irq_of_parse_and_map(np, i);
  204. if (irq == NO_IRQ)
  205. continue;
  206. irq_data = irq_get_irq_data(irq);
  207. if (!irq_data) {
  208. pr_err("%pOF: combiner-%d no irq_data for virq %d!\n",
  209. np, i, irq);
  210. continue;
  211. }
  212. hwirq = irq_data->hwirq;
  213. /*
  214. * Check that device tree provided something in the range
  215. * of the core priority interrupts (4 - 15).
  216. */
  217. if (hwirq < 4 || hwirq >= NR_PRIORITY_IRQS) {
  218. pr_err("%pOF: combiner-%d core irq %ld out of range!\n",
  219. np, i, hwirq);
  220. continue;
  221. }
  222. /* record the mapping */
  223. mapping[hwirq - 4] = i;
  224. pr_debug("%pOF: combiner-%d cascading to hwirq %ld\n",
  225. np, i, hwirq);
  226. cascade_data[i].pic = pic;
  227. cascade_data[i].index = i;
  228. /* mask and clear all events in combiner */
  229. soc_writel(~0, &pic->regs->evtmask[i]);
  230. soc_writel(~0, &pic->regs->evtclr[i]);
  231. irq_set_chained_handler_and_data(irq, megamod_irq_cascade,
  232. &cascade_data[i]);
  233. }
  234. /* Finally, set up the MUX registers */
  235. for (i = 0; i < NR_MUX_OUTPUTS; i++) {
  236. if (mapping[i] != IRQ_UNMAPPED) {
  237. pr_debug("%pOF: setting mux %d to priority %d\n",
  238. np, mapping[i], i + 4);
  239. set_megamod_mux(pic, mapping[i], i);
  240. }
  241. }
  242. return pic;
  243. error_free:
  244. kfree(pic);
  245. return NULL;
  246. }
  247. /*
  248. * Return next active event after ACK'ing it.
  249. * Return -1 if no events active.
  250. */
  251. static int get_exception(void)
  252. {
  253. int i, bit;
  254. u32 mask;
  255. for (i = 0; i < NR_COMBINERS; i++) {
  256. mask = soc_readl(&mm_pic->regs->mexpflag[i]);
  257. if (mask) {
  258. bit = __ffs(mask);
  259. soc_writel(1 << bit, &mm_pic->regs->evtclr[i]);
  260. return (i * 32) + bit;
  261. }
  262. }
  263. return -1;
  264. }
  265. static void assert_event(unsigned int val)
  266. {
  267. soc_writel(val, &mm_pic->regs->evtasrt);
  268. }
  269. void __init megamod_pic_init(void)
  270. {
  271. struct device_node *np;
  272. np = of_find_compatible_node(NULL, NULL, "ti,c64x+megamod-pic");
  273. if (!np)
  274. return;
  275. mm_pic = init_megamod_pic(np);
  276. of_node_put(np);
  277. soc_ops.get_exception = get_exception;
  278. soc_ops.assert_event = assert_event;
  279. return;
  280. }