cache.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2011 Texas Instruments Incorporated
  4. * Author: Mark Salter <msalter@redhat.com>
  5. */
  6. #include <linux/of.h>
  7. #include <linux/of_address.h>
  8. #include <linux/io.h>
  9. #include <asm/cache.h>
  10. #include <asm/soc.h>
  11. /*
  12. * Internal Memory Control Registers for caches
  13. */
  14. #define IMCR_CCFG 0x0000
  15. #define IMCR_L1PCFG 0x0020
  16. #define IMCR_L1PCC 0x0024
  17. #define IMCR_L1DCFG 0x0040
  18. #define IMCR_L1DCC 0x0044
  19. #define IMCR_L2ALLOC0 0x2000
  20. #define IMCR_L2ALLOC1 0x2004
  21. #define IMCR_L2ALLOC2 0x2008
  22. #define IMCR_L2ALLOC3 0x200c
  23. #define IMCR_L2WBAR 0x4000
  24. #define IMCR_L2WWC 0x4004
  25. #define IMCR_L2WIBAR 0x4010
  26. #define IMCR_L2WIWC 0x4014
  27. #define IMCR_L2IBAR 0x4018
  28. #define IMCR_L2IWC 0x401c
  29. #define IMCR_L1PIBAR 0x4020
  30. #define IMCR_L1PIWC 0x4024
  31. #define IMCR_L1DWIBAR 0x4030
  32. #define IMCR_L1DWIWC 0x4034
  33. #define IMCR_L1DWBAR 0x4040
  34. #define IMCR_L1DWWC 0x4044
  35. #define IMCR_L1DIBAR 0x4048
  36. #define IMCR_L1DIWC 0x404c
  37. #define IMCR_L2WB 0x5000
  38. #define IMCR_L2WBINV 0x5004
  39. #define IMCR_L2INV 0x5008
  40. #define IMCR_L1PINV 0x5028
  41. #define IMCR_L1DWB 0x5040
  42. #define IMCR_L1DWBINV 0x5044
  43. #define IMCR_L1DINV 0x5048
  44. #define IMCR_MAR_BASE 0x8000
  45. #define IMCR_MAR96_111 0x8180
  46. #define IMCR_MAR128_191 0x8200
  47. #define IMCR_MAR224_239 0x8380
  48. #define IMCR_L2MPFAR 0xa000
  49. #define IMCR_L2MPFSR 0xa004
  50. #define IMCR_L2MPFCR 0xa008
  51. #define IMCR_L2MPLK0 0xa100
  52. #define IMCR_L2MPLK1 0xa104
  53. #define IMCR_L2MPLK2 0xa108
  54. #define IMCR_L2MPLK3 0xa10c
  55. #define IMCR_L2MPLKCMD 0xa110
  56. #define IMCR_L2MPLKSTAT 0xa114
  57. #define IMCR_L2MPPA_BASE 0xa200
  58. #define IMCR_L1PMPFAR 0xa400
  59. #define IMCR_L1PMPFSR 0xa404
  60. #define IMCR_L1PMPFCR 0xa408
  61. #define IMCR_L1PMPLK0 0xa500
  62. #define IMCR_L1PMPLK1 0xa504
  63. #define IMCR_L1PMPLK2 0xa508
  64. #define IMCR_L1PMPLK3 0xa50c
  65. #define IMCR_L1PMPLKCMD 0xa510
  66. #define IMCR_L1PMPLKSTAT 0xa514
  67. #define IMCR_L1PMPPA_BASE 0xa600
  68. #define IMCR_L1DMPFAR 0xac00
  69. #define IMCR_L1DMPFSR 0xac04
  70. #define IMCR_L1DMPFCR 0xac08
  71. #define IMCR_L1DMPLK0 0xad00
  72. #define IMCR_L1DMPLK1 0xad04
  73. #define IMCR_L1DMPLK2 0xad08
  74. #define IMCR_L1DMPLK3 0xad0c
  75. #define IMCR_L1DMPLKCMD 0xad10
  76. #define IMCR_L1DMPLKSTAT 0xad14
  77. #define IMCR_L1DMPPA_BASE 0xae00
  78. #define IMCR_L2PDWAKE0 0xc040
  79. #define IMCR_L2PDWAKE1 0xc044
  80. #define IMCR_L2PDSLEEP0 0xc050
  81. #define IMCR_L2PDSLEEP1 0xc054
  82. #define IMCR_L2PDSTAT0 0xc060
  83. #define IMCR_L2PDSTAT1 0xc064
  84. /*
  85. * CCFG register values and bits
  86. */
  87. #define L2MODE_0K_CACHE 0x0
  88. #define L2MODE_32K_CACHE 0x1
  89. #define L2MODE_64K_CACHE 0x2
  90. #define L2MODE_128K_CACHE 0x3
  91. #define L2MODE_256K_CACHE 0x7
  92. #define L2PRIO_URGENT 0x0
  93. #define L2PRIO_HIGH 0x1
  94. #define L2PRIO_MEDIUM 0x2
  95. #define L2PRIO_LOW 0x3
  96. #define CCFG_ID 0x100 /* Invalidate L1P bit */
  97. #define CCFG_IP 0x200 /* Invalidate L1D bit */
  98. static void __iomem *cache_base;
  99. /*
  100. * L1 & L2 caches generic functions
  101. */
  102. #define imcr_get(reg) soc_readl(cache_base + (reg))
  103. #define imcr_set(reg, value) \
  104. do { \
  105. soc_writel((value), cache_base + (reg)); \
  106. soc_readl(cache_base + (reg)); \
  107. } while (0)
  108. static void cache_block_operation_wait(unsigned int wc_reg)
  109. {
  110. /* Wait for completion */
  111. while (imcr_get(wc_reg))
  112. cpu_relax();
  113. }
  114. static DEFINE_SPINLOCK(cache_lock);
  115. /*
  116. * Generic function to perform a block cache operation as
  117. * invalidate or writeback/invalidate
  118. */
  119. static void cache_block_operation(unsigned int *start,
  120. unsigned int *end,
  121. unsigned int bar_reg,
  122. unsigned int wc_reg)
  123. {
  124. unsigned long flags;
  125. unsigned int wcnt =
  126. (L2_CACHE_ALIGN_CNT((unsigned int) end)
  127. - L2_CACHE_ALIGN_LOW((unsigned int) start)) >> 2;
  128. unsigned int wc = 0;
  129. for (; wcnt; wcnt -= wc, start += wc) {
  130. loop:
  131. spin_lock_irqsave(&cache_lock, flags);
  132. /*
  133. * If another cache operation is occurring
  134. */
  135. if (unlikely(imcr_get(wc_reg))) {
  136. spin_unlock_irqrestore(&cache_lock, flags);
  137. /* Wait for previous operation completion */
  138. cache_block_operation_wait(wc_reg);
  139. /* Try again */
  140. goto loop;
  141. }
  142. imcr_set(bar_reg, L2_CACHE_ALIGN_LOW((unsigned int) start));
  143. if (wcnt > 0xffff)
  144. wc = 0xffff;
  145. else
  146. wc = wcnt;
  147. /* Set word count value in the WC register */
  148. imcr_set(wc_reg, wc & 0xffff);
  149. spin_unlock_irqrestore(&cache_lock, flags);
  150. /* Wait for completion */
  151. cache_block_operation_wait(wc_reg);
  152. }
  153. }
  154. static void cache_block_operation_nowait(unsigned int *start,
  155. unsigned int *end,
  156. unsigned int bar_reg,
  157. unsigned int wc_reg)
  158. {
  159. unsigned long flags;
  160. unsigned int wcnt =
  161. (L2_CACHE_ALIGN_CNT((unsigned int) end)
  162. - L2_CACHE_ALIGN_LOW((unsigned int) start)) >> 2;
  163. unsigned int wc = 0;
  164. for (; wcnt; wcnt -= wc, start += wc) {
  165. spin_lock_irqsave(&cache_lock, flags);
  166. imcr_set(bar_reg, L2_CACHE_ALIGN_LOW((unsigned int) start));
  167. if (wcnt > 0xffff)
  168. wc = 0xffff;
  169. else
  170. wc = wcnt;
  171. /* Set word count value in the WC register */
  172. imcr_set(wc_reg, wc & 0xffff);
  173. spin_unlock_irqrestore(&cache_lock, flags);
  174. /* Don't wait for completion on last cache operation */
  175. if (wcnt > 0xffff)
  176. cache_block_operation_wait(wc_reg);
  177. }
  178. }
  179. /*
  180. * L1 caches management
  181. */
  182. /*
  183. * Disable L1 caches
  184. */
  185. void L1_cache_off(void)
  186. {
  187. unsigned int dummy;
  188. imcr_set(IMCR_L1PCFG, 0);
  189. dummy = imcr_get(IMCR_L1PCFG);
  190. imcr_set(IMCR_L1DCFG, 0);
  191. dummy = imcr_get(IMCR_L1DCFG);
  192. }
  193. /*
  194. * Enable L1 caches
  195. */
  196. void L1_cache_on(void)
  197. {
  198. unsigned int dummy;
  199. imcr_set(IMCR_L1PCFG, 7);
  200. dummy = imcr_get(IMCR_L1PCFG);
  201. imcr_set(IMCR_L1DCFG, 7);
  202. dummy = imcr_get(IMCR_L1DCFG);
  203. }
  204. /*
  205. * L1P global-invalidate all
  206. */
  207. void L1P_cache_global_invalidate(void)
  208. {
  209. unsigned int set = 1;
  210. imcr_set(IMCR_L1PINV, set);
  211. while (imcr_get(IMCR_L1PINV) & 1)
  212. cpu_relax();
  213. }
  214. /*
  215. * L1D global-invalidate all
  216. *
  217. * Warning: this operation causes all updated data in L1D to
  218. * be discarded rather than written back to the lower levels of
  219. * memory
  220. */
  221. void L1D_cache_global_invalidate(void)
  222. {
  223. unsigned int set = 1;
  224. imcr_set(IMCR_L1DINV, set);
  225. while (imcr_get(IMCR_L1DINV) & 1)
  226. cpu_relax();
  227. }
  228. void L1D_cache_global_writeback(void)
  229. {
  230. unsigned int set = 1;
  231. imcr_set(IMCR_L1DWB, set);
  232. while (imcr_get(IMCR_L1DWB) & 1)
  233. cpu_relax();
  234. }
  235. void L1D_cache_global_writeback_invalidate(void)
  236. {
  237. unsigned int set = 1;
  238. imcr_set(IMCR_L1DWBINV, set);
  239. while (imcr_get(IMCR_L1DWBINV) & 1)
  240. cpu_relax();
  241. }
  242. /*
  243. * L2 caches management
  244. */
  245. /*
  246. * Set L2 operation mode
  247. */
  248. void L2_cache_set_mode(unsigned int mode)
  249. {
  250. unsigned int ccfg = imcr_get(IMCR_CCFG);
  251. /* Clear and set the L2MODE bits in CCFG */
  252. ccfg &= ~7;
  253. ccfg |= (mode & 7);
  254. imcr_set(IMCR_CCFG, ccfg);
  255. ccfg = imcr_get(IMCR_CCFG);
  256. }
  257. /*
  258. * L2 global-writeback and global-invalidate all
  259. */
  260. void L2_cache_global_writeback_invalidate(void)
  261. {
  262. imcr_set(IMCR_L2WBINV, 1);
  263. while (imcr_get(IMCR_L2WBINV))
  264. cpu_relax();
  265. }
  266. /*
  267. * L2 global-writeback all
  268. */
  269. void L2_cache_global_writeback(void)
  270. {
  271. imcr_set(IMCR_L2WB, 1);
  272. while (imcr_get(IMCR_L2WB))
  273. cpu_relax();
  274. }
  275. /*
  276. * Cacheability controls
  277. */
  278. void enable_caching(unsigned long start, unsigned long end)
  279. {
  280. unsigned int mar = IMCR_MAR_BASE + ((start >> 24) << 2);
  281. unsigned int mar_e = IMCR_MAR_BASE + ((end >> 24) << 2);
  282. for (; mar <= mar_e; mar += 4)
  283. imcr_set(mar, imcr_get(mar) | 1);
  284. }
  285. void disable_caching(unsigned long start, unsigned long end)
  286. {
  287. unsigned int mar = IMCR_MAR_BASE + ((start >> 24) << 2);
  288. unsigned int mar_e = IMCR_MAR_BASE + ((end >> 24) << 2);
  289. for (; mar <= mar_e; mar += 4)
  290. imcr_set(mar, imcr_get(mar) & ~1);
  291. }
  292. /*
  293. * L1 block operations
  294. */
  295. void L1P_cache_block_invalidate(unsigned int start, unsigned int end)
  296. {
  297. cache_block_operation((unsigned int *) start,
  298. (unsigned int *) end,
  299. IMCR_L1PIBAR, IMCR_L1PIWC);
  300. }
  301. EXPORT_SYMBOL(L1P_cache_block_invalidate);
  302. void L1D_cache_block_invalidate(unsigned int start, unsigned int end)
  303. {
  304. cache_block_operation((unsigned int *) start,
  305. (unsigned int *) end,
  306. IMCR_L1DIBAR, IMCR_L1DIWC);
  307. }
  308. void L1D_cache_block_writeback_invalidate(unsigned int start, unsigned int end)
  309. {
  310. cache_block_operation((unsigned int *) start,
  311. (unsigned int *) end,
  312. IMCR_L1DWIBAR, IMCR_L1DWIWC);
  313. }
  314. void L1D_cache_block_writeback(unsigned int start, unsigned int end)
  315. {
  316. cache_block_operation((unsigned int *) start,
  317. (unsigned int *) end,
  318. IMCR_L1DWBAR, IMCR_L1DWWC);
  319. }
  320. EXPORT_SYMBOL(L1D_cache_block_writeback);
  321. /*
  322. * L2 block operations
  323. */
  324. void L2_cache_block_invalidate(unsigned int start, unsigned int end)
  325. {
  326. cache_block_operation((unsigned int *) start,
  327. (unsigned int *) end,
  328. IMCR_L2IBAR, IMCR_L2IWC);
  329. }
  330. void L2_cache_block_writeback(unsigned int start, unsigned int end)
  331. {
  332. cache_block_operation((unsigned int *) start,
  333. (unsigned int *) end,
  334. IMCR_L2WBAR, IMCR_L2WWC);
  335. }
  336. void L2_cache_block_writeback_invalidate(unsigned int start, unsigned int end)
  337. {
  338. cache_block_operation((unsigned int *) start,
  339. (unsigned int *) end,
  340. IMCR_L2WIBAR, IMCR_L2WIWC);
  341. }
  342. void L2_cache_block_invalidate_nowait(unsigned int start, unsigned int end)
  343. {
  344. cache_block_operation_nowait((unsigned int *) start,
  345. (unsigned int *) end,
  346. IMCR_L2IBAR, IMCR_L2IWC);
  347. }
  348. void L2_cache_block_writeback_nowait(unsigned int start, unsigned int end)
  349. {
  350. cache_block_operation_nowait((unsigned int *) start,
  351. (unsigned int *) end,
  352. IMCR_L2WBAR, IMCR_L2WWC);
  353. }
  354. void L2_cache_block_writeback_invalidate_nowait(unsigned int start,
  355. unsigned int end)
  356. {
  357. cache_block_operation_nowait((unsigned int *) start,
  358. (unsigned int *) end,
  359. IMCR_L2WIBAR, IMCR_L2WIWC);
  360. }
  361. /*
  362. * L1 and L2 caches configuration
  363. */
  364. void __init c6x_cache_init(void)
  365. {
  366. struct device_node *node;
  367. node = of_find_compatible_node(NULL, NULL, "ti,c64x+cache");
  368. if (!node)
  369. return;
  370. cache_base = of_iomap(node, 0);
  371. of_node_put(node);
  372. if (!cache_base)
  373. return;
  374. /* Set L2 caches on the the whole L2 SRAM memory */
  375. L2_cache_set_mode(L2MODE_SIZE);
  376. /* Enable L1 */
  377. L1_cache_on();
  378. }