vectors.S 1.6 KB

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  1. ; SPDX-License-Identifier: GPL-2.0-only
  2. ;
  3. ; Port on Texas Instruments TMS320C6x architecture
  4. ;
  5. ; Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
  6. ; Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
  7. ;
  8. ; This section handles all the interrupt vector routines.
  9. ; At RESET the processor sets up the DRAM timing parameters and
  10. ; branches to the label _c_int00 which handles initialization for the C code.
  11. ;
  12. #define ALIGNMENT 5
  13. .macro IRQVEC name, handler
  14. .align ALIGNMENT
  15. .hidden \name
  16. .global \name
  17. \name:
  18. #ifdef CONFIG_C6X_BIG_KERNEL
  19. STW .D2T1 A0,*B15--[2]
  20. || MVKL .S1 \handler,A0
  21. MVKH .S1 \handler,A0
  22. B .S2X A0
  23. LDW .D2T1 *++B15[2],A0
  24. NOP 4
  25. NOP
  26. NOP
  27. .endm
  28. #else /* CONFIG_C6X_BIG_KERNEL */
  29. B .S2 \handler
  30. NOP
  31. NOP
  32. NOP
  33. NOP
  34. NOP
  35. NOP
  36. NOP
  37. .endm
  38. #endif /* CONFIG_C6X_BIG_KERNEL */
  39. .sect ".vectors","ax"
  40. .align ALIGNMENT
  41. .global RESET
  42. .hidden RESET
  43. RESET:
  44. #ifdef CONFIG_C6X_BIG_KERNEL
  45. MVKL .S1 _c_int00,A0 ; branch to _c_int00
  46. MVKH .S1 _c_int00,A0
  47. B .S2X A0
  48. #else
  49. B .S2 _c_int00
  50. NOP
  51. NOP
  52. #endif
  53. NOP
  54. NOP
  55. NOP
  56. NOP
  57. NOP
  58. IRQVEC NMI,_nmi_handler ; NMI interrupt
  59. IRQVEC AINT,_bad_interrupt ; reserved
  60. IRQVEC MSGINT,_bad_interrupt ; reserved
  61. IRQVEC INT4,_int4_handler
  62. IRQVEC INT5,_int5_handler
  63. IRQVEC INT6,_int6_handler
  64. IRQVEC INT7,_int7_handler
  65. IRQVEC INT8,_int8_handler
  66. IRQVEC INT9,_int9_handler
  67. IRQVEC INT10,_int10_handler
  68. IRQVEC INT11,_int11_handler
  69. IRQVEC INT12,_int12_handler
  70. IRQVEC INT13,_int13_handler
  71. IRQVEC INT14,_int14_handler
  72. IRQVEC INT15,_int15_handler