sys_compat.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Based on arch/arm/kernel/sys_arm.c
  4. *
  5. * Copyright (C) People who wrote linux/arch/i386/kernel/sys_i386.c
  6. * Copyright (C) 1995, 1996 Russell King.
  7. * Copyright (C) 2012 ARM Ltd.
  8. */
  9. #include <linux/compat.h>
  10. #include <linux/cpufeature.h>
  11. #include <linux/personality.h>
  12. #include <linux/sched.h>
  13. #include <linux/sched/signal.h>
  14. #include <linux/slab.h>
  15. #include <linux/syscalls.h>
  16. #include <linux/uaccess.h>
  17. #include <asm/cacheflush.h>
  18. #include <asm/system_misc.h>
  19. #include <asm/tlbflush.h>
  20. #include <asm/unistd.h>
  21. static long
  22. __do_compat_cache_op(unsigned long start, unsigned long end)
  23. {
  24. long ret;
  25. do {
  26. unsigned long chunk = min(PAGE_SIZE, end - start);
  27. if (fatal_signal_pending(current))
  28. return 0;
  29. if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
  30. /*
  31. * The workaround requires an inner-shareable tlbi.
  32. * We pick the reserved-ASID to minimise the impact.
  33. */
  34. __tlbi(aside1is, __TLBI_VADDR(0, 0));
  35. dsb(ish);
  36. }
  37. ret = __flush_cache_user_range(start, start + chunk);
  38. if (ret)
  39. return ret;
  40. cond_resched();
  41. start += chunk;
  42. } while (start < end);
  43. return 0;
  44. }
  45. static inline long
  46. do_compat_cache_op(unsigned long start, unsigned long end, int flags)
  47. {
  48. if (end < start || flags)
  49. return -EINVAL;
  50. if (!access_ok((const void __user *)start, end - start))
  51. return -EFAULT;
  52. return __do_compat_cache_op(start, end);
  53. }
  54. /*
  55. * Handle all unrecognised system calls.
  56. */
  57. long compat_arm_syscall(struct pt_regs *regs, int scno)
  58. {
  59. unsigned long addr;
  60. switch (scno) {
  61. /*
  62. * Flush a region from virtual address 'r0' to virtual address 'r1'
  63. * _exclusive_. There is no alignment requirement on either address;
  64. * user space does not need to know the hardware cache layout.
  65. *
  66. * r2 contains flags. It should ALWAYS be passed as ZERO until it
  67. * is defined to be something else. For now we ignore it, but may
  68. * the fires of hell burn in your belly if you break this rule. ;)
  69. *
  70. * (at a later date, we may want to allow this call to not flush
  71. * various aspects of the cache. Passing '0' will guarantee that
  72. * everything necessary gets flushed to maintain consistency in
  73. * the specified region).
  74. */
  75. case __ARM_NR_compat_cacheflush:
  76. return do_compat_cache_op(regs->regs[0], regs->regs[1], regs->regs[2]);
  77. case __ARM_NR_compat_set_tls:
  78. current->thread.uw.tp_value = regs->regs[0];
  79. /*
  80. * Protect against register corruption from context switch.
  81. * See comment in tls_thread_flush.
  82. */
  83. barrier();
  84. write_sysreg(regs->regs[0], tpidrro_el0);
  85. return 0;
  86. default:
  87. /*
  88. * Calls 0xf0xxx..0xf07ff are defined to return -ENOSYS
  89. * if not implemented, rather than raising SIGILL. This
  90. * way the calling program can gracefully determine whether
  91. * a feature is supported.
  92. */
  93. if (scno < __ARM_NR_COMPAT_END)
  94. return -ENOSYS;
  95. break;
  96. }
  97. addr = instruction_pointer(regs) - (compat_thumb_mode(regs) ? 2 : 4);
  98. arm64_notify_die("Oops - bad compat syscall(2)", regs,
  99. SIGILL, ILL_ILLTRP, addr, scno);
  100. return 0;
  101. }