setup.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Based on arch/arm/kernel/setup.c
  4. *
  5. * Copyright (C) 1995-2001 Russell King
  6. * Copyright (C) 2012 ARM Ltd.
  7. */
  8. #include <linux/acpi.h>
  9. #include <linux/export.h>
  10. #include <linux/kernel.h>
  11. #include <linux/stddef.h>
  12. #include <linux/ioport.h>
  13. #include <linux/delay.h>
  14. #include <linux/initrd.h>
  15. #include <linux/console.h>
  16. #include <linux/cache.h>
  17. #include <linux/screen_info.h>
  18. #include <linux/init.h>
  19. #include <linux/kexec.h>
  20. #include <linux/root_dev.h>
  21. #include <linux/cpu.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/smp.h>
  24. #include <linux/fs.h>
  25. #include <linux/proc_fs.h>
  26. #include <linux/memblock.h>
  27. #include <linux/of_fdt.h>
  28. #include <linux/efi.h>
  29. #include <linux/psci.h>
  30. #include <linux/sched/task.h>
  31. #include <linux/mm.h>
  32. #include <asm/acpi.h>
  33. #include <asm/fixmap.h>
  34. #include <asm/cpu.h>
  35. #include <asm/cputype.h>
  36. #include <asm/daifflags.h>
  37. #include <asm/elf.h>
  38. #include <asm/cpufeature.h>
  39. #include <asm/cpu_ops.h>
  40. #include <asm/kasan.h>
  41. #include <asm/numa.h>
  42. #include <asm/sections.h>
  43. #include <asm/setup.h>
  44. #include <asm/smp_plat.h>
  45. #include <asm/cacheflush.h>
  46. #include <asm/tlbflush.h>
  47. #include <asm/traps.h>
  48. #include <asm/efi.h>
  49. #include <asm/xen/hypervisor.h>
  50. #include <asm/mmu_context.h>
  51. static int num_standard_resources;
  52. static struct resource *standard_resources;
  53. phys_addr_t __fdt_pointer __initdata;
  54. /*
  55. * Standard memory resources
  56. */
  57. static struct resource mem_res[] = {
  58. {
  59. .name = "Kernel code",
  60. .start = 0,
  61. .end = 0,
  62. .flags = IORESOURCE_SYSTEM_RAM
  63. },
  64. {
  65. .name = "Kernel data",
  66. .start = 0,
  67. .end = 0,
  68. .flags = IORESOURCE_SYSTEM_RAM
  69. }
  70. };
  71. #define kernel_code mem_res[0]
  72. #define kernel_data mem_res[1]
  73. /*
  74. * The recorded values of x0 .. x3 upon kernel entry.
  75. */
  76. u64 __cacheline_aligned boot_args[4];
  77. void __init smp_setup_processor_id(void)
  78. {
  79. u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
  80. set_cpu_logical_map(0, mpidr);
  81. /*
  82. * clear __my_cpu_offset on boot CPU to avoid hang caused by
  83. * using percpu variable early, for example, lockdep will
  84. * access percpu variable inside lock_release
  85. */
  86. set_my_cpu_offset(0);
  87. pr_info("Booting Linux on physical CPU 0x%010lx [0x%08x]\n",
  88. (unsigned long)mpidr, read_cpuid_id());
  89. }
  90. bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
  91. {
  92. return phys_id == cpu_logical_map(cpu);
  93. }
  94. struct mpidr_hash mpidr_hash;
  95. /**
  96. * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
  97. * level in order to build a linear index from an
  98. * MPIDR value. Resulting algorithm is a collision
  99. * free hash carried out through shifting and ORing
  100. */
  101. static void __init smp_build_mpidr_hash(void)
  102. {
  103. u32 i, affinity, fs[4], bits[4], ls;
  104. u64 mask = 0;
  105. /*
  106. * Pre-scan the list of MPIDRS and filter out bits that do
  107. * not contribute to affinity levels, ie they never toggle.
  108. */
  109. for_each_possible_cpu(i)
  110. mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
  111. pr_debug("mask of set bits %#llx\n", mask);
  112. /*
  113. * Find and stash the last and first bit set at all affinity levels to
  114. * check how many bits are required to represent them.
  115. */
  116. for (i = 0; i < 4; i++) {
  117. affinity = MPIDR_AFFINITY_LEVEL(mask, i);
  118. /*
  119. * Find the MSB bit and LSB bits position
  120. * to determine how many bits are required
  121. * to express the affinity level.
  122. */
  123. ls = fls(affinity);
  124. fs[i] = affinity ? ffs(affinity) - 1 : 0;
  125. bits[i] = ls - fs[i];
  126. }
  127. /*
  128. * An index can be created from the MPIDR_EL1 by isolating the
  129. * significant bits at each affinity level and by shifting
  130. * them in order to compress the 32 bits values space to a
  131. * compressed set of values. This is equivalent to hashing
  132. * the MPIDR_EL1 through shifting and ORing. It is a collision free
  133. * hash though not minimal since some levels might contain a number
  134. * of CPUs that is not an exact power of 2 and their bit
  135. * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
  136. */
  137. mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
  138. mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
  139. mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
  140. (bits[1] + bits[0]);
  141. mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
  142. fs[3] - (bits[2] + bits[1] + bits[0]);
  143. mpidr_hash.mask = mask;
  144. mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
  145. pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
  146. mpidr_hash.shift_aff[0],
  147. mpidr_hash.shift_aff[1],
  148. mpidr_hash.shift_aff[2],
  149. mpidr_hash.shift_aff[3],
  150. mpidr_hash.mask,
  151. mpidr_hash.bits);
  152. /*
  153. * 4x is an arbitrary value used to warn on a hash table much bigger
  154. * than expected on most systems.
  155. */
  156. if (mpidr_hash_size() > 4 * num_possible_cpus())
  157. pr_warn("Large number of MPIDR hash buckets detected\n");
  158. }
  159. static void *early_fdt_ptr __initdata;
  160. void __init *get_early_fdt_ptr(void)
  161. {
  162. return early_fdt_ptr;
  163. }
  164. asmlinkage void __init early_fdt_map(u64 dt_phys)
  165. {
  166. int fdt_size;
  167. early_fixmap_init();
  168. early_fdt_ptr = fixmap_remap_fdt(dt_phys, &fdt_size, PAGE_KERNEL);
  169. }
  170. static void __init setup_machine_fdt(phys_addr_t dt_phys)
  171. {
  172. int size;
  173. void *dt_virt = fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL);
  174. const char *name;
  175. if (dt_virt)
  176. memblock_reserve(dt_phys, size);
  177. if (!dt_virt || !early_init_dt_scan(dt_virt)) {
  178. pr_crit("\n"
  179. "Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n"
  180. "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n"
  181. "\nPlease check your bootloader.",
  182. &dt_phys, dt_virt);
  183. while (true)
  184. cpu_relax();
  185. }
  186. /* Early fixups are done, map the FDT as read-only now */
  187. fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL_RO);
  188. name = of_flat_dt_get_machine_name();
  189. if (!name)
  190. return;
  191. pr_info("Machine model: %s\n", name);
  192. dump_stack_set_arch_desc("%s (DT)", name);
  193. }
  194. static void __init request_standard_resources(void)
  195. {
  196. struct memblock_region *region;
  197. struct resource *res;
  198. unsigned long i = 0;
  199. size_t res_size;
  200. kernel_code.start = __pa_symbol(_text);
  201. kernel_code.end = __pa_symbol(__init_begin - 1);
  202. kernel_data.start = __pa_symbol(_sdata);
  203. kernel_data.end = __pa_symbol(_end - 1);
  204. num_standard_resources = memblock.memory.cnt;
  205. res_size = num_standard_resources * sizeof(*standard_resources);
  206. standard_resources = memblock_alloc(res_size, SMP_CACHE_BYTES);
  207. if (!standard_resources)
  208. panic("%s: Failed to allocate %zu bytes\n", __func__, res_size);
  209. for_each_mem_region(region) {
  210. res = &standard_resources[i++];
  211. if (memblock_is_nomap(region)) {
  212. res->name = "reserved";
  213. res->flags = IORESOURCE_MEM;
  214. } else {
  215. res->name = "System RAM";
  216. res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
  217. }
  218. res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
  219. res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
  220. request_resource(&iomem_resource, res);
  221. if (kernel_code.start >= res->start &&
  222. kernel_code.end <= res->end)
  223. request_resource(res, &kernel_code);
  224. if (kernel_data.start >= res->start &&
  225. kernel_data.end <= res->end)
  226. request_resource(res, &kernel_data);
  227. #ifdef CONFIG_KEXEC_CORE
  228. /* Userspace will find "Crash kernel" region in /proc/iomem. */
  229. if (crashk_res.end && crashk_res.start >= res->start &&
  230. crashk_res.end <= res->end)
  231. request_resource(res, &crashk_res);
  232. #endif
  233. }
  234. }
  235. static int __init reserve_memblock_reserved_regions(void)
  236. {
  237. u64 i, j;
  238. for (i = 0; i < num_standard_resources; ++i) {
  239. struct resource *mem = &standard_resources[i];
  240. phys_addr_t r_start, r_end, mem_size = resource_size(mem);
  241. if (!memblock_is_region_reserved(mem->start, mem_size))
  242. continue;
  243. for_each_reserved_mem_range(j, &r_start, &r_end) {
  244. resource_size_t start, end;
  245. start = max(PFN_PHYS(PFN_DOWN(r_start)), mem->start);
  246. end = min(PFN_PHYS(PFN_UP(r_end)) - 1, mem->end);
  247. if (start > mem->end || end < mem->start)
  248. continue;
  249. reserve_region_with_split(mem, start, end, "reserved");
  250. }
  251. }
  252. return 0;
  253. }
  254. arch_initcall(reserve_memblock_reserved_regions);
  255. u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
  256. u64 cpu_logical_map(unsigned int cpu)
  257. {
  258. return __cpu_logical_map[cpu];
  259. }
  260. void __init __no_sanitize_address setup_arch(char **cmdline_p)
  261. {
  262. init_mm.start_code = (unsigned long) _text;
  263. init_mm.end_code = (unsigned long) _etext;
  264. init_mm.end_data = (unsigned long) _edata;
  265. init_mm.brk = (unsigned long) _end;
  266. *cmdline_p = boot_command_line;
  267. /*
  268. * If know now we are going to need KPTI then use non-global
  269. * mappings from the start, avoiding the cost of rewriting
  270. * everything later.
  271. */
  272. arm64_use_ng_mappings = kaslr_requires_kpti();
  273. early_fixmap_init();
  274. early_ioremap_init();
  275. setup_machine_fdt(__fdt_pointer);
  276. /*
  277. * Initialise the static keys early as they may be enabled by the
  278. * cpufeature code and early parameters.
  279. */
  280. jump_label_init();
  281. parse_early_param();
  282. /*
  283. * Unmask asynchronous aborts and fiq after bringing up possible
  284. * earlycon. (Report possible System Errors once we can report this
  285. * occurred).
  286. */
  287. local_daif_restore(DAIF_PROCCTX_NOIRQ);
  288. /*
  289. * TTBR0 is only used for the identity mapping at this stage. Make it
  290. * point to zero page to avoid speculatively fetching new entries.
  291. */
  292. cpu_uninstall_idmap();
  293. xen_early_init();
  294. efi_init();
  295. if (!efi_enabled(EFI_BOOT) && ((u64)_text % MIN_KIMG_ALIGN) != 0)
  296. pr_warn(FW_BUG "Kernel image misaligned at boot, please fix your bootloader!");
  297. arm64_memblock_init();
  298. paging_init();
  299. acpi_table_upgrade();
  300. /* Parse the ACPI tables for possible boot-time configuration */
  301. acpi_boot_table_init();
  302. if (acpi_disabled)
  303. unflatten_device_tree();
  304. bootmem_init();
  305. kasan_init();
  306. request_standard_resources();
  307. early_ioremap_reset();
  308. if (acpi_disabled)
  309. psci_dt_init();
  310. else
  311. psci_acpi_init();
  312. init_bootcpu_ops();
  313. smp_init_cpus();
  314. smp_build_mpidr_hash();
  315. /* Init percpu seeds for random tags after cpus are set up. */
  316. kasan_init_sw_tags();
  317. #ifdef CONFIG_ARM64_SW_TTBR0_PAN
  318. /*
  319. * Make sure init_thread_info.ttbr0 always generates translation
  320. * faults in case uaccess_enable() is inadvertently called by the init
  321. * thread.
  322. */
  323. init_task.thread_info.ttbr0 = phys_to_ttbr(__pa_symbol(reserved_pg_dir));
  324. #endif
  325. if (boot_args[1] || boot_args[2] || boot_args[3]) {
  326. pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n"
  327. "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n"
  328. "This indicates a broken bootloader or old kernel\n",
  329. boot_args[1], boot_args[2], boot_args[3]);
  330. }
  331. }
  332. static inline bool cpu_can_disable(unsigned int cpu)
  333. {
  334. #ifdef CONFIG_HOTPLUG_CPU
  335. const struct cpu_operations *ops = get_cpu_ops(cpu);
  336. if (ops && ops->cpu_can_disable)
  337. return ops->cpu_can_disable(cpu);
  338. #endif
  339. return false;
  340. }
  341. static int __init topology_init(void)
  342. {
  343. int i;
  344. for_each_online_node(i)
  345. register_one_node(i);
  346. for_each_possible_cpu(i) {
  347. struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
  348. cpu->hotpluggable = cpu_can_disable(i);
  349. register_cpu(cpu, i);
  350. }
  351. return 0;
  352. }
  353. subsys_initcall(topology_init);
  354. static void dump_kernel_offset(void)
  355. {
  356. const unsigned long offset = kaslr_offset();
  357. if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && offset > 0) {
  358. pr_emerg("Kernel Offset: 0x%lx from 0x%lx\n",
  359. offset, KIMAGE_VADDR);
  360. pr_emerg("PHYS_OFFSET: 0x%llx\n", PHYS_OFFSET);
  361. } else {
  362. pr_emerg("Kernel Offset: disabled\n");
  363. }
  364. }
  365. static int arm64_panic_block_dump(struct notifier_block *self,
  366. unsigned long v, void *p)
  367. {
  368. dump_kernel_offset();
  369. dump_cpu_features();
  370. dump_mem_limit();
  371. return 0;
  372. }
  373. static struct notifier_block arm64_panic_block = {
  374. .notifier_call = arm64_panic_block_dump
  375. };
  376. static int __init register_arm64_panic_block(void)
  377. {
  378. atomic_notifier_chain_register(&panic_notifier_list,
  379. &arm64_panic_block);
  380. return 0;
  381. }
  382. device_initcall(register_arm64_panic_block);