perf_event.c 39 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ARMv8 PMUv3 Performance Events handling code.
  4. *
  5. * Copyright (C) 2012 ARM Limited
  6. * Author: Will Deacon <will.deacon@arm.com>
  7. *
  8. * This code is based heavily on the ARMv7 perf event code.
  9. */
  10. #include <asm/irq_regs.h>
  11. #include <asm/perf_event.h>
  12. #include <asm/sysreg.h>
  13. #include <asm/virt.h>
  14. #include <clocksource/arm_arch_timer.h>
  15. #include <linux/acpi.h>
  16. #include <linux/clocksource.h>
  17. #include <linux/kvm_host.h>
  18. #include <linux/of.h>
  19. #include <linux/perf/arm_pmu.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/sched_clock.h>
  22. #include <linux/smp.h>
  23. /* ARMv8 Cortex-A53 specific event types. */
  24. #define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
  25. /* ARMv8 Cavium ThunderX specific event types. */
  26. #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST 0xE9
  27. #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS 0xEA
  28. #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS 0xEB
  29. #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC
  30. #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED
  31. /*
  32. * ARMv8 Architectural defined events, not all of these may
  33. * be supported on any given implementation. Unsupported events will
  34. * be disabled at run-time based on the PMCEID registers.
  35. */
  36. static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
  37. PERF_MAP_ALL_UNSUPPORTED,
  38. [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
  39. [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
  40. [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
  41. [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
  42. [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
  43. [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
  44. [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
  45. [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
  46. [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
  47. };
  48. static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  49. [PERF_COUNT_HW_CACHE_OP_MAX]
  50. [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  51. PERF_CACHE_MAP_ALL_UNSUPPORTED,
  52. [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
  53. [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
  54. [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
  55. [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
  56. [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
  57. [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
  58. [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
  59. [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
  60. [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
  61. [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
  62. [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
  63. [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
  64. };
  65. static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  66. [PERF_COUNT_HW_CACHE_OP_MAX]
  67. [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  68. PERF_CACHE_MAP_ALL_UNSUPPORTED,
  69. [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
  70. [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
  71. [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
  72. };
  73. static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  74. [PERF_COUNT_HW_CACHE_OP_MAX]
  75. [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  76. PERF_CACHE_MAP_ALL_UNSUPPORTED,
  77. [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
  78. [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
  79. [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
  80. [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
  81. [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
  82. [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
  83. [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
  84. [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
  85. };
  86. static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  87. [PERF_COUNT_HW_CACHE_OP_MAX]
  88. [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  89. PERF_CACHE_MAP_ALL_UNSUPPORTED,
  90. [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
  91. [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
  92. };
  93. static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  94. [PERF_COUNT_HW_CACHE_OP_MAX]
  95. [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  96. PERF_CACHE_MAP_ALL_UNSUPPORTED,
  97. [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
  98. [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
  99. [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
  100. [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
  101. [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
  102. [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
  103. [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
  104. [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
  105. [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
  106. [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
  107. [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
  108. [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
  109. };
  110. static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  111. [PERF_COUNT_HW_CACHE_OP_MAX]
  112. [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  113. PERF_CACHE_MAP_ALL_UNSUPPORTED,
  114. [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
  115. [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
  116. [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
  117. [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
  118. [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
  119. [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
  120. [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
  121. [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
  122. [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
  123. [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
  124. };
  125. static ssize_t
  126. armv8pmu_events_sysfs_show(struct device *dev,
  127. struct device_attribute *attr, char *page)
  128. {
  129. struct perf_pmu_events_attr *pmu_attr;
  130. pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
  131. return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
  132. }
  133. #define ARMV8_EVENT_ATTR(name, config) \
  134. (&((struct perf_pmu_events_attr) { \
  135. .attr = __ATTR(name, 0444, armv8pmu_events_sysfs_show, NULL), \
  136. .id = config, \
  137. }).attr.attr)
  138. static struct attribute *armv8_pmuv3_event_attrs[] = {
  139. ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR),
  140. ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL),
  141. ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL),
  142. ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL),
  143. ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE),
  144. ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL),
  145. ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED),
  146. ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED),
  147. ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED),
  148. ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN),
  149. ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN),
  150. ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED),
  151. ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED),
  152. ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED),
  153. ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED),
  154. ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED),
  155. ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED),
  156. ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES),
  157. ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED),
  158. ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS),
  159. ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE),
  160. ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB),
  161. ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE),
  162. ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL),
  163. ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB),
  164. ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS),
  165. ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR),
  166. ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC),
  167. ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED),
  168. ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES),
  169. /* Don't expose the chain event in /sys, since it's useless in isolation */
  170. ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE),
  171. ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE),
  172. ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED),
  173. ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED),
  174. ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND),
  175. ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND),
  176. ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB),
  177. ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB),
  178. ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE),
  179. ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL),
  180. ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE),
  181. ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL),
  182. ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE),
  183. ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB),
  184. ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL),
  185. ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL),
  186. ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB),
  187. ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB),
  188. ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS),
  189. ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE),
  190. ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS),
  191. ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK),
  192. ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK),
  193. ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
  194. ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
  195. ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
  196. ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
  197. ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
  198. ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
  199. ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
  200. ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
  201. ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
  202. ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
  203. ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
  204. ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
  205. ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
  206. ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
  207. ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
  208. ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
  209. ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
  210. ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
  211. ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
  212. ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
  213. ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
  214. ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
  215. ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
  216. ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
  217. ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
  218. ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
  219. NULL,
  220. };
  221. static umode_t
  222. armv8pmu_event_attr_is_visible(struct kobject *kobj,
  223. struct attribute *attr, int unused)
  224. {
  225. struct device *dev = kobj_to_dev(kobj);
  226. struct pmu *pmu = dev_get_drvdata(dev);
  227. struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
  228. struct perf_pmu_events_attr *pmu_attr;
  229. pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
  230. if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
  231. test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
  232. return attr->mode;
  233. if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) {
  234. u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
  235. if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
  236. test_bit(id, cpu_pmu->pmceid_ext_bitmap))
  237. return attr->mode;
  238. }
  239. return 0;
  240. }
  241. static struct attribute_group armv8_pmuv3_events_attr_group = {
  242. .name = "events",
  243. .attrs = armv8_pmuv3_event_attrs,
  244. .is_visible = armv8pmu_event_attr_is_visible,
  245. };
  246. PMU_FORMAT_ATTR(event, "config:0-15");
  247. PMU_FORMAT_ATTR(long, "config1:0");
  248. static inline bool armv8pmu_event_is_64bit(struct perf_event *event)
  249. {
  250. return event->attr.config1 & 0x1;
  251. }
  252. static struct attribute *armv8_pmuv3_format_attrs[] = {
  253. &format_attr_event.attr,
  254. &format_attr_long.attr,
  255. NULL,
  256. };
  257. static struct attribute_group armv8_pmuv3_format_attr_group = {
  258. .name = "format",
  259. .attrs = armv8_pmuv3_format_attrs,
  260. };
  261. static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
  262. char *page)
  263. {
  264. struct pmu *pmu = dev_get_drvdata(dev);
  265. struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
  266. u32 slots = cpu_pmu->reg_pmmir & ARMV8_PMU_SLOTS_MASK;
  267. return sysfs_emit(page, "0x%08x\n", slots);
  268. }
  269. static DEVICE_ATTR_RO(slots);
  270. static struct attribute *armv8_pmuv3_caps_attrs[] = {
  271. &dev_attr_slots.attr,
  272. NULL,
  273. };
  274. static struct attribute_group armv8_pmuv3_caps_attr_group = {
  275. .name = "caps",
  276. .attrs = armv8_pmuv3_caps_attrs,
  277. };
  278. /*
  279. * Perf Events' indices
  280. */
  281. #define ARMV8_IDX_CYCLE_COUNTER 0
  282. #define ARMV8_IDX_COUNTER0 1
  283. /*
  284. * We unconditionally enable ARMv8.5-PMU long event counter support
  285. * (64-bit events) where supported. Indicate if this arm_pmu has long
  286. * event counter support.
  287. */
  288. static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu)
  289. {
  290. return (cpu_pmu->pmuver >= ID_AA64DFR0_PMUVER_8_5);
  291. }
  292. /*
  293. * We must chain two programmable counters for 64 bit events,
  294. * except when we have allocated the 64bit cycle counter (for CPU
  295. * cycles event). This must be called only when the event has
  296. * a counter allocated.
  297. */
  298. static inline bool armv8pmu_event_is_chained(struct perf_event *event)
  299. {
  300. int idx = event->hw.idx;
  301. struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
  302. return !WARN_ON(idx < 0) &&
  303. armv8pmu_event_is_64bit(event) &&
  304. !armv8pmu_has_long_event(cpu_pmu) &&
  305. (idx != ARMV8_IDX_CYCLE_COUNTER);
  306. }
  307. /*
  308. * ARMv8 low level PMU access
  309. */
  310. /*
  311. * Perf Event to low level counters mapping
  312. */
  313. #define ARMV8_IDX_TO_COUNTER(x) \
  314. (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
  315. /*
  316. * This code is really good
  317. */
  318. #define PMEVN_CASE(n, case_macro) \
  319. case n: case_macro(n); break
  320. #define PMEVN_SWITCH(x, case_macro) \
  321. do { \
  322. switch (x) { \
  323. PMEVN_CASE(0, case_macro); \
  324. PMEVN_CASE(1, case_macro); \
  325. PMEVN_CASE(2, case_macro); \
  326. PMEVN_CASE(3, case_macro); \
  327. PMEVN_CASE(4, case_macro); \
  328. PMEVN_CASE(5, case_macro); \
  329. PMEVN_CASE(6, case_macro); \
  330. PMEVN_CASE(7, case_macro); \
  331. PMEVN_CASE(8, case_macro); \
  332. PMEVN_CASE(9, case_macro); \
  333. PMEVN_CASE(10, case_macro); \
  334. PMEVN_CASE(11, case_macro); \
  335. PMEVN_CASE(12, case_macro); \
  336. PMEVN_CASE(13, case_macro); \
  337. PMEVN_CASE(14, case_macro); \
  338. PMEVN_CASE(15, case_macro); \
  339. PMEVN_CASE(16, case_macro); \
  340. PMEVN_CASE(17, case_macro); \
  341. PMEVN_CASE(18, case_macro); \
  342. PMEVN_CASE(19, case_macro); \
  343. PMEVN_CASE(20, case_macro); \
  344. PMEVN_CASE(21, case_macro); \
  345. PMEVN_CASE(22, case_macro); \
  346. PMEVN_CASE(23, case_macro); \
  347. PMEVN_CASE(24, case_macro); \
  348. PMEVN_CASE(25, case_macro); \
  349. PMEVN_CASE(26, case_macro); \
  350. PMEVN_CASE(27, case_macro); \
  351. PMEVN_CASE(28, case_macro); \
  352. PMEVN_CASE(29, case_macro); \
  353. PMEVN_CASE(30, case_macro); \
  354. default: WARN(1, "Invalid PMEV* index\n"); \
  355. } \
  356. } while (0)
  357. #define RETURN_READ_PMEVCNTRN(n) \
  358. return read_sysreg(pmevcntr##n##_el0)
  359. static unsigned long read_pmevcntrn(int n)
  360. {
  361. PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
  362. return 0;
  363. }
  364. #define WRITE_PMEVCNTRN(n) \
  365. write_sysreg(val, pmevcntr##n##_el0)
  366. static void write_pmevcntrn(int n, unsigned long val)
  367. {
  368. PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
  369. }
  370. #define WRITE_PMEVTYPERN(n) \
  371. write_sysreg(val, pmevtyper##n##_el0)
  372. static void write_pmevtypern(int n, unsigned long val)
  373. {
  374. PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
  375. }
  376. static inline u32 armv8pmu_pmcr_read(void)
  377. {
  378. return read_sysreg(pmcr_el0);
  379. }
  380. static inline void armv8pmu_pmcr_write(u32 val)
  381. {
  382. val &= ARMV8_PMU_PMCR_MASK;
  383. isb();
  384. write_sysreg(val, pmcr_el0);
  385. }
  386. static inline int armv8pmu_has_overflowed(u32 pmovsr)
  387. {
  388. return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
  389. }
  390. static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
  391. {
  392. return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
  393. }
  394. static inline u64 armv8pmu_read_evcntr(int idx)
  395. {
  396. u32 counter = ARMV8_IDX_TO_COUNTER(idx);
  397. return read_pmevcntrn(counter);
  398. }
  399. static inline u64 armv8pmu_read_hw_counter(struct perf_event *event)
  400. {
  401. int idx = event->hw.idx;
  402. u64 val = 0;
  403. val = armv8pmu_read_evcntr(idx);
  404. if (armv8pmu_event_is_chained(event))
  405. val = (val << 32) | armv8pmu_read_evcntr(idx - 1);
  406. return val;
  407. }
  408. /*
  409. * The cycle counter is always a 64-bit counter. When ARMV8_PMU_PMCR_LP
  410. * is set the event counters also become 64-bit counters. Unless the
  411. * user has requested a long counter (attr.config1) then we want to
  412. * interrupt upon 32-bit overflow - we achieve this by applying a bias.
  413. */
  414. static bool armv8pmu_event_needs_bias(struct perf_event *event)
  415. {
  416. struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
  417. struct hw_perf_event *hwc = &event->hw;
  418. int idx = hwc->idx;
  419. if (armv8pmu_event_is_64bit(event))
  420. return false;
  421. if (armv8pmu_has_long_event(cpu_pmu) ||
  422. idx == ARMV8_IDX_CYCLE_COUNTER)
  423. return true;
  424. return false;
  425. }
  426. static u64 armv8pmu_bias_long_counter(struct perf_event *event, u64 value)
  427. {
  428. if (armv8pmu_event_needs_bias(event))
  429. value |= GENMASK(63, 32);
  430. return value;
  431. }
  432. static u64 armv8pmu_unbias_long_counter(struct perf_event *event, u64 value)
  433. {
  434. if (armv8pmu_event_needs_bias(event))
  435. value &= ~GENMASK(63, 32);
  436. return value;
  437. }
  438. static u64 armv8pmu_read_counter(struct perf_event *event)
  439. {
  440. struct hw_perf_event *hwc = &event->hw;
  441. int idx = hwc->idx;
  442. u64 value = 0;
  443. if (idx == ARMV8_IDX_CYCLE_COUNTER)
  444. value = read_sysreg(pmccntr_el0);
  445. else
  446. value = armv8pmu_read_hw_counter(event);
  447. return armv8pmu_unbias_long_counter(event, value);
  448. }
  449. static inline void armv8pmu_write_evcntr(int idx, u64 value)
  450. {
  451. u32 counter = ARMV8_IDX_TO_COUNTER(idx);
  452. write_pmevcntrn(counter, value);
  453. }
  454. static inline void armv8pmu_write_hw_counter(struct perf_event *event,
  455. u64 value)
  456. {
  457. int idx = event->hw.idx;
  458. if (armv8pmu_event_is_chained(event)) {
  459. armv8pmu_write_evcntr(idx, upper_32_bits(value));
  460. armv8pmu_write_evcntr(idx - 1, lower_32_bits(value));
  461. } else {
  462. armv8pmu_write_evcntr(idx, value);
  463. }
  464. }
  465. static void armv8pmu_write_counter(struct perf_event *event, u64 value)
  466. {
  467. struct hw_perf_event *hwc = &event->hw;
  468. int idx = hwc->idx;
  469. value = armv8pmu_bias_long_counter(event, value);
  470. if (idx == ARMV8_IDX_CYCLE_COUNTER)
  471. write_sysreg(value, pmccntr_el0);
  472. else
  473. armv8pmu_write_hw_counter(event, value);
  474. }
  475. static inline void armv8pmu_write_evtype(int idx, u32 val)
  476. {
  477. u32 counter = ARMV8_IDX_TO_COUNTER(idx);
  478. val &= ARMV8_PMU_EVTYPE_MASK;
  479. write_pmevtypern(counter, val);
  480. }
  481. static inline void armv8pmu_write_event_type(struct perf_event *event)
  482. {
  483. struct hw_perf_event *hwc = &event->hw;
  484. int idx = hwc->idx;
  485. /*
  486. * For chained events, the low counter is programmed to count
  487. * the event of interest and the high counter is programmed
  488. * with CHAIN event code with filters set to count at all ELs.
  489. */
  490. if (armv8pmu_event_is_chained(event)) {
  491. u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN |
  492. ARMV8_PMU_INCLUDE_EL2;
  493. armv8pmu_write_evtype(idx - 1, hwc->config_base);
  494. armv8pmu_write_evtype(idx, chain_evt);
  495. } else {
  496. if (idx == ARMV8_IDX_CYCLE_COUNTER)
  497. write_sysreg(hwc->config_base, pmccfiltr_el0);
  498. else
  499. armv8pmu_write_evtype(idx, hwc->config_base);
  500. }
  501. }
  502. static u32 armv8pmu_event_cnten_mask(struct perf_event *event)
  503. {
  504. int counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
  505. u32 mask = BIT(counter);
  506. if (armv8pmu_event_is_chained(event))
  507. mask |= BIT(counter - 1);
  508. return mask;
  509. }
  510. static inline void armv8pmu_enable_counter(u32 mask)
  511. {
  512. /*
  513. * Make sure event configuration register writes are visible before we
  514. * enable the counter.
  515. * */
  516. isb();
  517. write_sysreg(mask, pmcntenset_el0);
  518. }
  519. static inline void armv8pmu_enable_event_counter(struct perf_event *event)
  520. {
  521. struct perf_event_attr *attr = &event->attr;
  522. u32 mask = armv8pmu_event_cnten_mask(event);
  523. kvm_set_pmu_events(mask, attr);
  524. /* We rely on the hypervisor switch code to enable guest counters */
  525. if (!kvm_pmu_counter_deferred(attr))
  526. armv8pmu_enable_counter(mask);
  527. }
  528. static inline void armv8pmu_disable_counter(u32 mask)
  529. {
  530. write_sysreg(mask, pmcntenclr_el0);
  531. /*
  532. * Make sure the effects of disabling the counter are visible before we
  533. * start configuring the event.
  534. */
  535. isb();
  536. }
  537. static inline void armv8pmu_disable_event_counter(struct perf_event *event)
  538. {
  539. struct perf_event_attr *attr = &event->attr;
  540. u32 mask = armv8pmu_event_cnten_mask(event);
  541. kvm_clr_pmu_events(mask);
  542. /* We rely on the hypervisor switch code to disable guest counters */
  543. if (!kvm_pmu_counter_deferred(attr))
  544. armv8pmu_disable_counter(mask);
  545. }
  546. static inline void armv8pmu_enable_intens(u32 mask)
  547. {
  548. write_sysreg(mask, pmintenset_el1);
  549. }
  550. static inline void armv8pmu_enable_event_irq(struct perf_event *event)
  551. {
  552. u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
  553. armv8pmu_enable_intens(BIT(counter));
  554. }
  555. static inline void armv8pmu_disable_intens(u32 mask)
  556. {
  557. write_sysreg(mask, pmintenclr_el1);
  558. isb();
  559. /* Clear the overflow flag in case an interrupt is pending. */
  560. write_sysreg(mask, pmovsclr_el0);
  561. isb();
  562. }
  563. static inline void armv8pmu_disable_event_irq(struct perf_event *event)
  564. {
  565. u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
  566. armv8pmu_disable_intens(BIT(counter));
  567. }
  568. static inline u32 armv8pmu_getreset_flags(void)
  569. {
  570. u32 value;
  571. /* Read */
  572. value = read_sysreg(pmovsclr_el0);
  573. /* Write to clear flags */
  574. value &= ARMV8_PMU_OVSR_MASK;
  575. write_sysreg(value, pmovsclr_el0);
  576. return value;
  577. }
  578. static void armv8pmu_enable_event(struct perf_event *event)
  579. {
  580. /*
  581. * Enable counter and interrupt, and set the counter to count
  582. * the event that we're interested in.
  583. */
  584. /*
  585. * Disable counter
  586. */
  587. armv8pmu_disable_event_counter(event);
  588. /*
  589. * Set event.
  590. */
  591. armv8pmu_write_event_type(event);
  592. /*
  593. * Enable interrupt for this counter
  594. */
  595. armv8pmu_enable_event_irq(event);
  596. /*
  597. * Enable counter
  598. */
  599. armv8pmu_enable_event_counter(event);
  600. }
  601. static void armv8pmu_disable_event(struct perf_event *event)
  602. {
  603. /*
  604. * Disable counter
  605. */
  606. armv8pmu_disable_event_counter(event);
  607. /*
  608. * Disable interrupt for this counter
  609. */
  610. armv8pmu_disable_event_irq(event);
  611. }
  612. static void armv8pmu_start(struct arm_pmu *cpu_pmu)
  613. {
  614. /* Enable all counters */
  615. armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
  616. }
  617. static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
  618. {
  619. /* Disable all counters */
  620. armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
  621. }
  622. static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
  623. {
  624. u32 pmovsr;
  625. struct perf_sample_data data;
  626. struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
  627. struct pt_regs *regs;
  628. int idx;
  629. /*
  630. * Get and reset the IRQ flags
  631. */
  632. pmovsr = armv8pmu_getreset_flags();
  633. /*
  634. * Did an overflow occur?
  635. */
  636. if (!armv8pmu_has_overflowed(pmovsr))
  637. return IRQ_NONE;
  638. /*
  639. * Handle the counter(s) overflow(s)
  640. */
  641. regs = get_irq_regs();
  642. /*
  643. * Stop the PMU while processing the counter overflows
  644. * to prevent skews in group events.
  645. */
  646. armv8pmu_stop(cpu_pmu);
  647. for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
  648. struct perf_event *event = cpuc->events[idx];
  649. struct hw_perf_event *hwc;
  650. /* Ignore if we don't have an event. */
  651. if (!event)
  652. continue;
  653. /*
  654. * We have a single interrupt for all counters. Check that
  655. * each counter has overflowed before we process it.
  656. */
  657. if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
  658. continue;
  659. hwc = &event->hw;
  660. armpmu_event_update(event);
  661. perf_sample_data_init(&data, 0, hwc->last_period);
  662. if (!armpmu_event_set_period(event))
  663. continue;
  664. /*
  665. * Perf event overflow will queue the processing of the event as
  666. * an irq_work which will be taken care of in the handling of
  667. * IPI_IRQ_WORK.
  668. */
  669. if (perf_event_overflow(event, &data, regs))
  670. cpu_pmu->disable(event);
  671. }
  672. armv8pmu_start(cpu_pmu);
  673. return IRQ_HANDLED;
  674. }
  675. static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc,
  676. struct arm_pmu *cpu_pmu)
  677. {
  678. int idx;
  679. for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; idx ++) {
  680. if (!test_and_set_bit(idx, cpuc->used_mask))
  681. return idx;
  682. }
  683. return -EAGAIN;
  684. }
  685. static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,
  686. struct arm_pmu *cpu_pmu)
  687. {
  688. int idx;
  689. /*
  690. * Chaining requires two consecutive event counters, where
  691. * the lower idx must be even.
  692. */
  693. for (idx = ARMV8_IDX_COUNTER0 + 1; idx < cpu_pmu->num_events; idx += 2) {
  694. if (!test_and_set_bit(idx, cpuc->used_mask)) {
  695. /* Check if the preceding even counter is available */
  696. if (!test_and_set_bit(idx - 1, cpuc->used_mask))
  697. return idx;
  698. /* Release the Odd counter */
  699. clear_bit(idx, cpuc->used_mask);
  700. }
  701. }
  702. return -EAGAIN;
  703. }
  704. static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
  705. struct perf_event *event)
  706. {
  707. struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
  708. struct hw_perf_event *hwc = &event->hw;
  709. unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
  710. /* Always prefer to place a cycle counter into the cycle counter. */
  711. if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
  712. if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
  713. return ARMV8_IDX_CYCLE_COUNTER;
  714. }
  715. /*
  716. * Otherwise use events counters
  717. */
  718. if (armv8pmu_event_is_64bit(event) &&
  719. !armv8pmu_has_long_event(cpu_pmu))
  720. return armv8pmu_get_chain_idx(cpuc, cpu_pmu);
  721. else
  722. return armv8pmu_get_single_idx(cpuc, cpu_pmu);
  723. }
  724. static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc,
  725. struct perf_event *event)
  726. {
  727. int idx = event->hw.idx;
  728. clear_bit(idx, cpuc->used_mask);
  729. if (armv8pmu_event_is_chained(event))
  730. clear_bit(idx - 1, cpuc->used_mask);
  731. }
  732. /*
  733. * Add an event filter to a given event.
  734. */
  735. static int armv8pmu_set_event_filter(struct hw_perf_event *event,
  736. struct perf_event_attr *attr)
  737. {
  738. unsigned long config_base = 0;
  739. if (attr->exclude_idle)
  740. return -EPERM;
  741. /*
  742. * If we're running in hyp mode, then we *are* the hypervisor.
  743. * Therefore we ignore exclude_hv in this configuration, since
  744. * there's no hypervisor to sample anyway. This is consistent
  745. * with other architectures (x86 and Power).
  746. */
  747. if (is_kernel_in_hyp_mode()) {
  748. if (!attr->exclude_kernel && !attr->exclude_host)
  749. config_base |= ARMV8_PMU_INCLUDE_EL2;
  750. if (attr->exclude_guest)
  751. config_base |= ARMV8_PMU_EXCLUDE_EL1;
  752. if (attr->exclude_host)
  753. config_base |= ARMV8_PMU_EXCLUDE_EL0;
  754. } else {
  755. if (!attr->exclude_hv && !attr->exclude_host)
  756. config_base |= ARMV8_PMU_INCLUDE_EL2;
  757. }
  758. /*
  759. * Filter out !VHE kernels and guest kernels
  760. */
  761. if (attr->exclude_kernel)
  762. config_base |= ARMV8_PMU_EXCLUDE_EL1;
  763. if (attr->exclude_user)
  764. config_base |= ARMV8_PMU_EXCLUDE_EL0;
  765. /*
  766. * Install the filter into config_base as this is used to
  767. * construct the event type.
  768. */
  769. event->config_base = config_base;
  770. return 0;
  771. }
  772. static int armv8pmu_filter_match(struct perf_event *event)
  773. {
  774. unsigned long evtype = event->hw.config_base & ARMV8_PMU_EVTYPE_EVENT;
  775. return evtype != ARMV8_PMUV3_PERFCTR_CHAIN;
  776. }
  777. static void armv8pmu_reset(void *info)
  778. {
  779. struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
  780. u32 pmcr;
  781. /* The counter and interrupt enable registers are unknown at reset. */
  782. armv8pmu_disable_counter(U32_MAX);
  783. armv8pmu_disable_intens(U32_MAX);
  784. /* Clear the counters we flip at guest entry/exit */
  785. kvm_clr_pmu_events(U32_MAX);
  786. /*
  787. * Initialize & Reset PMNC. Request overflow interrupt for
  788. * 64 bit cycle counter but cheat in armv8pmu_write_counter().
  789. */
  790. pmcr = ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC;
  791. /* Enable long event counter support where available */
  792. if (armv8pmu_has_long_event(cpu_pmu))
  793. pmcr |= ARMV8_PMU_PMCR_LP;
  794. armv8pmu_pmcr_write(pmcr);
  795. }
  796. static int __armv8_pmuv3_map_event(struct perf_event *event,
  797. const unsigned (*extra_event_map)
  798. [PERF_COUNT_HW_MAX],
  799. const unsigned (*extra_cache_map)
  800. [PERF_COUNT_HW_CACHE_MAX]
  801. [PERF_COUNT_HW_CACHE_OP_MAX]
  802. [PERF_COUNT_HW_CACHE_RESULT_MAX])
  803. {
  804. int hw_event_id;
  805. struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
  806. hw_event_id = armpmu_map_event(event, &armv8_pmuv3_perf_map,
  807. &armv8_pmuv3_perf_cache_map,
  808. ARMV8_PMU_EVTYPE_EVENT);
  809. if (armv8pmu_event_is_64bit(event))
  810. event->hw.flags |= ARMPMU_EVT_64BIT;
  811. /* Only expose micro/arch events supported by this PMU */
  812. if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
  813. && test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
  814. return hw_event_id;
  815. }
  816. return armpmu_map_event(event, extra_event_map, extra_cache_map,
  817. ARMV8_PMU_EVTYPE_EVENT);
  818. }
  819. static int armv8_pmuv3_map_event(struct perf_event *event)
  820. {
  821. return __armv8_pmuv3_map_event(event, NULL, NULL);
  822. }
  823. static int armv8_a53_map_event(struct perf_event *event)
  824. {
  825. return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map);
  826. }
  827. static int armv8_a57_map_event(struct perf_event *event)
  828. {
  829. return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map);
  830. }
  831. static int armv8_a73_map_event(struct perf_event *event)
  832. {
  833. return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map);
  834. }
  835. static int armv8_thunder_map_event(struct perf_event *event)
  836. {
  837. return __armv8_pmuv3_map_event(event, NULL,
  838. &armv8_thunder_perf_cache_map);
  839. }
  840. static int armv8_vulcan_map_event(struct perf_event *event)
  841. {
  842. return __armv8_pmuv3_map_event(event, NULL,
  843. &armv8_vulcan_perf_cache_map);
  844. }
  845. struct armv8pmu_probe_info {
  846. struct arm_pmu *pmu;
  847. bool present;
  848. };
  849. static void __armv8pmu_probe_pmu(void *info)
  850. {
  851. struct armv8pmu_probe_info *probe = info;
  852. struct arm_pmu *cpu_pmu = probe->pmu;
  853. u64 dfr0;
  854. u64 pmceid_raw[2];
  855. u32 pmceid[2];
  856. int pmuver;
  857. dfr0 = read_sysreg(id_aa64dfr0_el1);
  858. pmuver = cpuid_feature_extract_unsigned_field(dfr0,
  859. ID_AA64DFR0_PMUVER_SHIFT);
  860. if (pmuver == 0xf || pmuver == 0)
  861. return;
  862. cpu_pmu->pmuver = pmuver;
  863. probe->present = true;
  864. /* Read the nb of CNTx counters supported from PMNC */
  865. cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
  866. & ARMV8_PMU_PMCR_N_MASK;
  867. /* Add the CPU cycles counter */
  868. cpu_pmu->num_events += 1;
  869. pmceid[0] = pmceid_raw[0] = read_sysreg(pmceid0_el0);
  870. pmceid[1] = pmceid_raw[1] = read_sysreg(pmceid1_el0);
  871. bitmap_from_arr32(cpu_pmu->pmceid_bitmap,
  872. pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
  873. pmceid[0] = pmceid_raw[0] >> 32;
  874. pmceid[1] = pmceid_raw[1] >> 32;
  875. bitmap_from_arr32(cpu_pmu->pmceid_ext_bitmap,
  876. pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
  877. /* store PMMIR_EL1 register for sysfs */
  878. if (pmuver >= ID_AA64DFR0_PMUVER_8_4 && (pmceid_raw[1] & BIT(31)))
  879. cpu_pmu->reg_pmmir = read_cpuid(PMMIR_EL1);
  880. else
  881. cpu_pmu->reg_pmmir = 0;
  882. }
  883. static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
  884. {
  885. struct armv8pmu_probe_info probe = {
  886. .pmu = cpu_pmu,
  887. .present = false,
  888. };
  889. int ret;
  890. ret = smp_call_function_any(&cpu_pmu->supported_cpus,
  891. __armv8pmu_probe_pmu,
  892. &probe, 1);
  893. if (ret)
  894. return ret;
  895. return probe.present ? 0 : -ENODEV;
  896. }
  897. static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
  898. int (*map_event)(struct perf_event *event),
  899. const struct attribute_group *events,
  900. const struct attribute_group *format,
  901. const struct attribute_group *caps)
  902. {
  903. int ret = armv8pmu_probe_pmu(cpu_pmu);
  904. if (ret)
  905. return ret;
  906. cpu_pmu->handle_irq = armv8pmu_handle_irq;
  907. cpu_pmu->enable = armv8pmu_enable_event;
  908. cpu_pmu->disable = armv8pmu_disable_event;
  909. cpu_pmu->read_counter = armv8pmu_read_counter;
  910. cpu_pmu->write_counter = armv8pmu_write_counter;
  911. cpu_pmu->get_event_idx = armv8pmu_get_event_idx;
  912. cpu_pmu->clear_event_idx = armv8pmu_clear_event_idx;
  913. cpu_pmu->start = armv8pmu_start;
  914. cpu_pmu->stop = armv8pmu_stop;
  915. cpu_pmu->reset = armv8pmu_reset;
  916. cpu_pmu->set_event_filter = armv8pmu_set_event_filter;
  917. cpu_pmu->filter_match = armv8pmu_filter_match;
  918. cpu_pmu->name = name;
  919. cpu_pmu->map_event = map_event;
  920. cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?
  921. events : &armv8_pmuv3_events_attr_group;
  922. cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
  923. format : &armv8_pmuv3_format_attr_group;
  924. cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ?
  925. caps : &armv8_pmuv3_caps_attr_group;
  926. return 0;
  927. }
  928. static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
  929. int (*map_event)(struct perf_event *event))
  930. {
  931. return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL);
  932. }
  933. static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
  934. {
  935. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3",
  936. armv8_pmuv3_map_event);
  937. }
  938. static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
  939. {
  940. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34",
  941. armv8_pmuv3_map_event);
  942. }
  943. static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
  944. {
  945. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a35",
  946. armv8_a53_map_event);
  947. }
  948. static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
  949. {
  950. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a53",
  951. armv8_a53_map_event);
  952. }
  953. static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
  954. {
  955. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55",
  956. armv8_pmuv3_map_event);
  957. }
  958. static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
  959. {
  960. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57",
  961. armv8_a57_map_event);
  962. }
  963. static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
  964. {
  965. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65",
  966. armv8_pmuv3_map_event);
  967. }
  968. static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
  969. {
  970. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72",
  971. armv8_a57_map_event);
  972. }
  973. static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
  974. {
  975. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a73",
  976. armv8_a73_map_event);
  977. }
  978. static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
  979. {
  980. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75",
  981. armv8_pmuv3_map_event);
  982. }
  983. static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
  984. {
  985. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76",
  986. armv8_pmuv3_map_event);
  987. }
  988. static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
  989. {
  990. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77",
  991. armv8_pmuv3_map_event);
  992. }
  993. static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
  994. {
  995. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1",
  996. armv8_pmuv3_map_event);
  997. }
  998. static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
  999. {
  1000. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1",
  1001. armv8_pmuv3_map_event);
  1002. }
  1003. static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
  1004. {
  1005. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
  1006. armv8_thunder_map_event);
  1007. }
  1008. static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
  1009. {
  1010. return armv8_pmu_init_nogroups(cpu_pmu, "armv8_brcm_vulcan",
  1011. armv8_vulcan_map_event);
  1012. }
  1013. static const struct of_device_id armv8_pmu_of_device_ids[] = {
  1014. {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init},
  1015. {.compatible = "arm,cortex-a34-pmu", .data = armv8_a34_pmu_init},
  1016. {.compatible = "arm,cortex-a35-pmu", .data = armv8_a35_pmu_init},
  1017. {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
  1018. {.compatible = "arm,cortex-a55-pmu", .data = armv8_a55_pmu_init},
  1019. {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
  1020. {.compatible = "arm,cortex-a65-pmu", .data = armv8_a65_pmu_init},
  1021. {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
  1022. {.compatible = "arm,cortex-a73-pmu", .data = armv8_a73_pmu_init},
  1023. {.compatible = "arm,cortex-a75-pmu", .data = armv8_a75_pmu_init},
  1024. {.compatible = "arm,cortex-a76-pmu", .data = armv8_a76_pmu_init},
  1025. {.compatible = "arm,cortex-a77-pmu", .data = armv8_a77_pmu_init},
  1026. {.compatible = "arm,neoverse-e1-pmu", .data = armv8_e1_pmu_init},
  1027. {.compatible = "arm,neoverse-n1-pmu", .data = armv8_n1_pmu_init},
  1028. {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
  1029. {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
  1030. {},
  1031. };
  1032. static int armv8_pmu_device_probe(struct platform_device *pdev)
  1033. {
  1034. return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
  1035. }
  1036. static struct platform_driver armv8_pmu_driver = {
  1037. .driver = {
  1038. .name = ARMV8_PMU_PDEV_NAME,
  1039. .of_match_table = armv8_pmu_of_device_ids,
  1040. .suppress_bind_attrs = true,
  1041. },
  1042. .probe = armv8_pmu_device_probe,
  1043. };
  1044. static int __init armv8_pmu_driver_init(void)
  1045. {
  1046. if (acpi_disabled)
  1047. return platform_driver_register(&armv8_pmu_driver);
  1048. else
  1049. return arm_pmu_acpi_probe(armv8_pmuv3_init);
  1050. }
  1051. device_initcall(armv8_pmu_driver_init)
  1052. void arch_perf_update_userpage(struct perf_event *event,
  1053. struct perf_event_mmap_page *userpg, u64 now)
  1054. {
  1055. struct clock_read_data *rd;
  1056. unsigned int seq;
  1057. u64 ns;
  1058. userpg->cap_user_time = 0;
  1059. userpg->cap_user_time_zero = 0;
  1060. userpg->cap_user_time_short = 0;
  1061. do {
  1062. rd = sched_clock_read_begin(&seq);
  1063. if (rd->read_sched_clock != arch_timer_read_counter)
  1064. return;
  1065. userpg->time_mult = rd->mult;
  1066. userpg->time_shift = rd->shift;
  1067. userpg->time_zero = rd->epoch_ns;
  1068. userpg->time_cycles = rd->epoch_cyc;
  1069. userpg->time_mask = rd->sched_clock_mask;
  1070. /*
  1071. * Subtract the cycle base, such that software that
  1072. * doesn't know about cap_user_time_short still 'works'
  1073. * assuming no wraps.
  1074. */
  1075. ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift);
  1076. userpg->time_zero -= ns;
  1077. } while (sched_clock_read_retry(seq));
  1078. userpg->time_offset = userpg->time_zero - now;
  1079. /*
  1080. * time_shift is not expected to be greater than 31 due to
  1081. * the original published conversion algorithm shifting a
  1082. * 32-bit value (now specifies a 64-bit value) - refer
  1083. * perf_event_mmap_page documentation in perf_event.h.
  1084. */
  1085. if (userpg->time_shift == 32) {
  1086. userpg->time_shift = 31;
  1087. userpg->time_mult >>= 1;
  1088. }
  1089. /*
  1090. * Internal timekeeping for enabled/running/stopped times
  1091. * is always computed with the sched_clock.
  1092. */
  1093. userpg->cap_user_time = 1;
  1094. userpg->cap_user_time_zero = 1;
  1095. userpg->cap_user_time_short = 1;
  1096. }