hyp-stub.S 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Hypervisor stub
  4. *
  5. * Copyright (C) 2012 ARM Ltd.
  6. * Author: Marc Zyngier <marc.zyngier@arm.com>
  7. */
  8. #include <linux/init.h>
  9. #include <linux/linkage.h>
  10. #include <asm/assembler.h>
  11. #include <asm/el2_setup.h>
  12. #include <asm/kvm_arm.h>
  13. #include <asm/kvm_asm.h>
  14. #include <asm/ptrace.h>
  15. #include <asm/virt.h>
  16. .text
  17. .pushsection .hyp.text, "ax"
  18. .align 11
  19. SYM_CODE_START(__hyp_stub_vectors)
  20. ventry el2_sync_invalid // Synchronous EL2t
  21. ventry el2_irq_invalid // IRQ EL2t
  22. ventry el2_fiq_invalid // FIQ EL2t
  23. ventry el2_error_invalid // Error EL2t
  24. ventry el2_sync_invalid // Synchronous EL2h
  25. ventry el2_irq_invalid // IRQ EL2h
  26. ventry el2_fiq_invalid // FIQ EL2h
  27. ventry el2_error_invalid // Error EL2h
  28. ventry el1_sync // Synchronous 64-bit EL1
  29. ventry el1_irq_invalid // IRQ 64-bit EL1
  30. ventry el1_fiq_invalid // FIQ 64-bit EL1
  31. ventry el1_error_invalid // Error 64-bit EL1
  32. ventry el1_sync_invalid // Synchronous 32-bit EL1
  33. ventry el1_irq_invalid // IRQ 32-bit EL1
  34. ventry el1_fiq_invalid // FIQ 32-bit EL1
  35. ventry el1_error_invalid // Error 32-bit EL1
  36. SYM_CODE_END(__hyp_stub_vectors)
  37. .align 11
  38. SYM_CODE_START_LOCAL(el1_sync)
  39. cmp x0, #HVC_SET_VECTORS
  40. b.ne 1f
  41. msr vbar_el2, x1
  42. b 9f
  43. 1: cmp x0, #HVC_VHE_RESTART
  44. b.eq mutate_to_vhe
  45. 2: cmp x0, #HVC_SOFT_RESTART
  46. b.ne 3f
  47. mov x0, x2
  48. mov x2, x4
  49. mov x4, x1
  50. mov x1, x3
  51. br x4 // no return
  52. 3: cmp x0, #HVC_RESET_VECTORS
  53. beq 9f // Nothing to reset!
  54. /* Someone called kvm_call_hyp() against the hyp-stub... */
  55. mov_q x0, HVC_STUB_ERR
  56. eret
  57. 9: mov x0, xzr
  58. eret
  59. SYM_CODE_END(el1_sync)
  60. // nVHE? No way! Give me the real thing!
  61. SYM_CODE_START_LOCAL(mutate_to_vhe)
  62. // Sanity check: MMU *must* be off
  63. mrs x1, sctlr_el2
  64. tbnz x1, #0, 1f
  65. // Needs to be VHE capable, obviously
  66. mrs x1, id_aa64mmfr1_el1
  67. ubfx x1, x1, #ID_AA64MMFR1_VHE_SHIFT, #4
  68. cbz x1, 1f
  69. // Check whether VHE is disabled from the command line
  70. adr_l x1, id_aa64mmfr1_override
  71. ldr x2, [x1, FTR_OVR_VAL_OFFSET]
  72. ldr x1, [x1, FTR_OVR_MASK_OFFSET]
  73. ubfx x2, x2, #ID_AA64MMFR1_VHE_SHIFT, #4
  74. ubfx x1, x1, #ID_AA64MMFR1_VHE_SHIFT, #4
  75. cmp x1, xzr
  76. and x2, x2, x1
  77. csinv x2, x2, xzr, ne
  78. cbnz x2, 2f
  79. 1: mov_q x0, HVC_STUB_ERR
  80. eret
  81. 2:
  82. // Engage the VHE magic!
  83. mov_q x0, HCR_HOST_VHE_FLAGS
  84. msr hcr_el2, x0
  85. isb
  86. // Use the EL1 allocated stack, per-cpu offset
  87. mrs x0, sp_el1
  88. mov sp, x0
  89. mrs x0, tpidr_el1
  90. msr tpidr_el2, x0
  91. // FP configuration, vectors
  92. mrs_s x0, SYS_CPACR_EL12
  93. msr cpacr_el1, x0
  94. mrs_s x0, SYS_VBAR_EL12
  95. msr vbar_el1, x0
  96. // Use EL2 translations for SPE & TRBE and disable access from EL1
  97. mrs x0, mdcr_el2
  98. bic x0, x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
  99. bic x0, x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)
  100. msr mdcr_el2, x0
  101. // Transfer the MM state from EL1 to EL2
  102. mrs_s x0, SYS_TCR_EL12
  103. msr tcr_el1, x0
  104. mrs_s x0, SYS_TTBR0_EL12
  105. msr ttbr0_el1, x0
  106. mrs_s x0, SYS_TTBR1_EL12
  107. msr ttbr1_el1, x0
  108. mrs_s x0, SYS_MAIR_EL12
  109. msr mair_el1, x0
  110. isb
  111. // Hack the exception return to stay at EL2
  112. mrs x0, spsr_el1
  113. and x0, x0, #~PSR_MODE_MASK
  114. mov x1, #PSR_MODE_EL2h
  115. orr x0, x0, x1
  116. msr spsr_el1, x0
  117. b enter_vhe
  118. SYM_CODE_END(mutate_to_vhe)
  119. // At the point where we reach enter_vhe(), we run with
  120. // the MMU off (which is enforced by mutate_to_vhe()).
  121. // We thus need to be in the idmap, or everything will
  122. // explode when enabling the MMU.
  123. .pushsection .idmap.text, "ax"
  124. SYM_CODE_START_LOCAL(enter_vhe)
  125. // Invalidate TLBs before enabling the MMU
  126. tlbi vmalle1
  127. dsb nsh
  128. isb
  129. // Enable the EL2 S1 MMU, as set up from EL1
  130. mrs_s x0, SYS_SCTLR_EL12
  131. set_sctlr_el1 x0
  132. // Disable the EL1 S1 MMU for a good measure
  133. mov_q x0, INIT_SCTLR_EL1_MMU_OFF
  134. msr_s SYS_SCTLR_EL12, x0
  135. mov x0, xzr
  136. eret
  137. SYM_CODE_END(enter_vhe)
  138. .popsection
  139. .macro invalid_vector label
  140. SYM_CODE_START_LOCAL(\label)
  141. b \label
  142. SYM_CODE_END(\label)
  143. .endm
  144. invalid_vector el2_sync_invalid
  145. invalid_vector el2_irq_invalid
  146. invalid_vector el2_fiq_invalid
  147. invalid_vector el2_error_invalid
  148. invalid_vector el1_sync_invalid
  149. invalid_vector el1_irq_invalid
  150. invalid_vector el1_fiq_invalid
  151. invalid_vector el1_error_invalid
  152. .popsection
  153. /*
  154. * __hyp_set_vectors: Call this after boot to set the initial hypervisor
  155. * vectors as part of hypervisor installation. On an SMP system, this should
  156. * be called on each CPU.
  157. *
  158. * x0 must be the physical address of the new vector table, and must be
  159. * 2KB aligned.
  160. *
  161. * Before calling this, you must check that the stub hypervisor is installed
  162. * everywhere, by waiting for any secondary CPUs to be brought up and then
  163. * checking that is_hyp_mode_available() is true.
  164. *
  165. * If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
  166. * something else went wrong... in such cases, trying to install a new
  167. * hypervisor is unlikely to work as desired.
  168. *
  169. * When you call into your shiny new hypervisor, sp_el2 will contain junk,
  170. * so you will need to set that to something sensible at the new hypervisor's
  171. * initialisation entry point.
  172. */
  173. SYM_FUNC_START(__hyp_set_vectors)
  174. mov x1, x0
  175. mov x0, #HVC_SET_VECTORS
  176. hvc #0
  177. ret
  178. SYM_FUNC_END(__hyp_set_vectors)
  179. SYM_FUNC_START(__hyp_reset_vectors)
  180. mov x0, #HVC_RESET_VECTORS
  181. hvc #0
  182. ret
  183. SYM_FUNC_END(__hyp_reset_vectors)
  184. /*
  185. * Entry point to switch to VHE if deemed capable
  186. */
  187. SYM_FUNC_START(switch_to_vhe)
  188. #ifdef CONFIG_ARM64_VHE
  189. // Need to have booted at EL2
  190. adr_l x1, __boot_cpu_mode
  191. ldr w0, [x1]
  192. cmp w0, #BOOT_CPU_MODE_EL2
  193. b.ne 1f
  194. // and still be at EL1
  195. mrs x0, CurrentEL
  196. cmp x0, #CurrentEL_EL1
  197. b.ne 1f
  198. // Turn the world upside down
  199. mov x0, #HVC_VHE_RESTART
  200. hvc #0
  201. 1:
  202. #endif
  203. ret
  204. SYM_FUNC_END(switch_to_vhe)