hibernate-asm.S 4.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Hibernate low-level support
  4. *
  5. * Copyright (C) 2016 ARM Ltd.
  6. * Author: James Morse <james.morse@arm.com>
  7. */
  8. #include <linux/linkage.h>
  9. #include <linux/errno.h>
  10. #include <asm/asm-offsets.h>
  11. #include <asm/assembler.h>
  12. #include <asm/cputype.h>
  13. #include <asm/memory.h>
  14. #include <asm/page.h>
  15. #include <asm/virt.h>
  16. /*
  17. * To prevent the possibility of old and new partial table walks being visible
  18. * in the tlb, switch the ttbr to a zero page when we invalidate the old
  19. * records. D4.7.1 'General TLB maintenance requirements' in ARM DDI 0487A.i
  20. * Even switching to our copied tables will cause a changed output address at
  21. * each stage of the walk.
  22. */
  23. .macro break_before_make_ttbr_switch zero_page, page_table, tmp, tmp2
  24. phys_to_ttbr \tmp, \zero_page
  25. msr ttbr1_el1, \tmp
  26. isb
  27. tlbi vmalle1
  28. dsb nsh
  29. phys_to_ttbr \tmp, \page_table
  30. offset_ttbr1 \tmp, \tmp2
  31. msr ttbr1_el1, \tmp
  32. isb
  33. .endm
  34. /*
  35. * Resume from hibernate
  36. *
  37. * Loads temporary page tables then restores the memory image.
  38. * Finally branches to cpu_resume() to restore the state saved by
  39. * swsusp_arch_suspend().
  40. *
  41. * Because this code has to be copied to a 'safe' page, it can't call out to
  42. * other functions by PC-relative address. Also remember that it may be
  43. * mid-way through over-writing other functions. For this reason it contains
  44. * code from flush_icache_range() and uses the copy_page() macro.
  45. *
  46. * This 'safe' page is mapped via ttbr0, and executed from there. This function
  47. * switches to a copy of the linear map in ttbr1, performs the restore, then
  48. * switches ttbr1 to the original kernel's swapper_pg_dir.
  49. *
  50. * All of memory gets written to, including code. We need to clean the kernel
  51. * text to the Point of Coherence (PoC) before secondary cores can be booted.
  52. * Because the kernel modules and executable pages mapped to user space are
  53. * also written as data, we clean all pages we touch to the Point of
  54. * Unification (PoU).
  55. *
  56. * x0: physical address of temporary page tables
  57. * x1: physical address of swapper page tables
  58. * x2: address of cpu_resume
  59. * x3: linear map address of restore_pblist in the current kernel
  60. * x4: physical address of __hyp_stub_vectors, or 0
  61. * x5: physical address of a zero page that remains zero after resume
  62. */
  63. .pushsection ".hibernate_exit.text", "ax"
  64. SYM_CODE_START(swsusp_arch_suspend_exit)
  65. /*
  66. * We execute from ttbr0, change ttbr1 to our copied linear map tables
  67. * with a break-before-make via the zero page
  68. */
  69. break_before_make_ttbr_switch x5, x0, x6, x8
  70. mov x21, x1
  71. mov x30, x2
  72. mov x24, x4
  73. mov x25, x5
  74. /* walk the restore_pblist and use copy_page() to over-write memory */
  75. mov x19, x3
  76. 1: ldr x10, [x19, #HIBERN_PBE_ORIG]
  77. mov x0, x10
  78. ldr x1, [x19, #HIBERN_PBE_ADDR]
  79. copy_page x0, x1, x2, x3, x4, x5, x6, x7, x8, x9
  80. add x1, x10, #PAGE_SIZE
  81. /* Clean the copied page to PoU - based on flush_icache_range() */
  82. raw_dcache_line_size x2, x3
  83. sub x3, x2, #1
  84. bic x4, x10, x3
  85. 2: dc cvau, x4 /* clean D line / unified line */
  86. add x4, x4, x2
  87. cmp x4, x1
  88. b.lo 2b
  89. ldr x19, [x19, #HIBERN_PBE_NEXT]
  90. cbnz x19, 1b
  91. dsb ish /* wait for PoU cleaning to finish */
  92. /* switch to the restored kernels page tables */
  93. break_before_make_ttbr_switch x25, x21, x6, x8
  94. ic ialluis
  95. dsb ish
  96. isb
  97. cbz x24, 3f /* Do we need to re-initialise EL2? */
  98. hvc #0
  99. 3: ret
  100. SYM_CODE_END(swsusp_arch_suspend_exit)
  101. /*
  102. * Restore the hyp stub.
  103. * This must be done before the hibernate page is unmapped by _cpu_resume(),
  104. * but happens before any of the hyp-stub's code is cleaned to PoC.
  105. *
  106. * x24: The physical address of __hyp_stub_vectors
  107. */
  108. SYM_CODE_START_LOCAL(el1_sync)
  109. msr vbar_el2, x24
  110. eret
  111. SYM_CODE_END(el1_sync)
  112. .macro invalid_vector label
  113. SYM_CODE_START_LOCAL(\label)
  114. b \label
  115. SYM_CODE_END(\label)
  116. .endm
  117. invalid_vector el2_sync_invalid
  118. invalid_vector el2_irq_invalid
  119. invalid_vector el2_fiq_invalid
  120. invalid_vector el2_error_invalid
  121. invalid_vector el1_sync_invalid
  122. invalid_vector el1_irq_invalid
  123. invalid_vector el1_fiq_invalid
  124. invalid_vector el1_error_invalid
  125. /* el2 vectors - switch el2 here while we restore the memory image. */
  126. .align 11
  127. SYM_CODE_START(hibernate_el2_vectors)
  128. ventry el2_sync_invalid // Synchronous EL2t
  129. ventry el2_irq_invalid // IRQ EL2t
  130. ventry el2_fiq_invalid // FIQ EL2t
  131. ventry el2_error_invalid // Error EL2t
  132. ventry el2_sync_invalid // Synchronous EL2h
  133. ventry el2_irq_invalid // IRQ EL2h
  134. ventry el2_fiq_invalid // FIQ EL2h
  135. ventry el2_error_invalid // Error EL2h
  136. ventry el1_sync // Synchronous 64-bit EL1
  137. ventry el1_irq_invalid // IRQ 64-bit EL1
  138. ventry el1_fiq_invalid // FIQ 64-bit EL1
  139. ventry el1_error_invalid // Error 64-bit EL1
  140. ventry el1_sync_invalid // Synchronous 32-bit EL1
  141. ventry el1_irq_invalid // IRQ 32-bit EL1
  142. ventry el1_fiq_invalid // FIQ 32-bit EL1
  143. ventry el1_error_invalid // Error 32-bit EL1
  144. SYM_CODE_END(hibernate_el2_vectors)
  145. .popsection