cpuinfo.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Record and handle CPU attributes.
  4. *
  5. * Copyright (C) 2014 ARM Ltd.
  6. */
  7. #include <asm/arch_timer.h>
  8. #include <asm/cache.h>
  9. #include <asm/cpu.h>
  10. #include <asm/cputype.h>
  11. #include <asm/cpufeature.h>
  12. #include <asm/fpsimd.h>
  13. #include <linux/bitops.h>
  14. #include <linux/bug.h>
  15. #include <linux/compat.h>
  16. #include <linux/elf.h>
  17. #include <linux/init.h>
  18. #include <linux/kernel.h>
  19. #include <linux/personality.h>
  20. #include <linux/preempt.h>
  21. #include <linux/printk.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/sched.h>
  24. #include <linux/smp.h>
  25. #include <linux/delay.h>
  26. /*
  27. * In case the boot CPU is hotpluggable, we record its initial state and
  28. * current state separately. Certain system registers may contain different
  29. * values depending on configuration at or after reset.
  30. */
  31. DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
  32. static struct cpuinfo_arm64 boot_cpu_data;
  33. static const char *icache_policy_str[] = {
  34. [ICACHE_POLICY_VPIPT] = "VPIPT",
  35. [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
  36. [ICACHE_POLICY_VIPT] = "VIPT",
  37. [ICACHE_POLICY_PIPT] = "PIPT",
  38. };
  39. unsigned long __icache_flags;
  40. static const char *const hwcap_str[] = {
  41. [KERNEL_HWCAP_FP] = "fp",
  42. [KERNEL_HWCAP_ASIMD] = "asimd",
  43. [KERNEL_HWCAP_EVTSTRM] = "evtstrm",
  44. [KERNEL_HWCAP_AES] = "aes",
  45. [KERNEL_HWCAP_PMULL] = "pmull",
  46. [KERNEL_HWCAP_SHA1] = "sha1",
  47. [KERNEL_HWCAP_SHA2] = "sha2",
  48. [KERNEL_HWCAP_CRC32] = "crc32",
  49. [KERNEL_HWCAP_ATOMICS] = "atomics",
  50. [KERNEL_HWCAP_FPHP] = "fphp",
  51. [KERNEL_HWCAP_ASIMDHP] = "asimdhp",
  52. [KERNEL_HWCAP_CPUID] = "cpuid",
  53. [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm",
  54. [KERNEL_HWCAP_JSCVT] = "jscvt",
  55. [KERNEL_HWCAP_FCMA] = "fcma",
  56. [KERNEL_HWCAP_LRCPC] = "lrcpc",
  57. [KERNEL_HWCAP_DCPOP] = "dcpop",
  58. [KERNEL_HWCAP_SHA3] = "sha3",
  59. [KERNEL_HWCAP_SM3] = "sm3",
  60. [KERNEL_HWCAP_SM4] = "sm4",
  61. [KERNEL_HWCAP_ASIMDDP] = "asimddp",
  62. [KERNEL_HWCAP_SHA512] = "sha512",
  63. [KERNEL_HWCAP_SVE] = "sve",
  64. [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm",
  65. [KERNEL_HWCAP_DIT] = "dit",
  66. [KERNEL_HWCAP_USCAT] = "uscat",
  67. [KERNEL_HWCAP_ILRCPC] = "ilrcpc",
  68. [KERNEL_HWCAP_FLAGM] = "flagm",
  69. [KERNEL_HWCAP_SSBS] = "ssbs",
  70. [KERNEL_HWCAP_SB] = "sb",
  71. [KERNEL_HWCAP_PACA] = "paca",
  72. [KERNEL_HWCAP_PACG] = "pacg",
  73. [KERNEL_HWCAP_DCPODP] = "dcpodp",
  74. [KERNEL_HWCAP_SVE2] = "sve2",
  75. [KERNEL_HWCAP_SVEAES] = "sveaes",
  76. [KERNEL_HWCAP_SVEPMULL] = "svepmull",
  77. [KERNEL_HWCAP_SVEBITPERM] = "svebitperm",
  78. [KERNEL_HWCAP_SVESHA3] = "svesha3",
  79. [KERNEL_HWCAP_SVESM4] = "svesm4",
  80. [KERNEL_HWCAP_FLAGM2] = "flagm2",
  81. [KERNEL_HWCAP_FRINT] = "frint",
  82. [KERNEL_HWCAP_SVEI8MM] = "svei8mm",
  83. [KERNEL_HWCAP_SVEF32MM] = "svef32mm",
  84. [KERNEL_HWCAP_SVEF64MM] = "svef64mm",
  85. [KERNEL_HWCAP_SVEBF16] = "svebf16",
  86. [KERNEL_HWCAP_I8MM] = "i8mm",
  87. [KERNEL_HWCAP_BF16] = "bf16",
  88. [KERNEL_HWCAP_DGH] = "dgh",
  89. [KERNEL_HWCAP_RNG] = "rng",
  90. [KERNEL_HWCAP_BTI] = "bti",
  91. [KERNEL_HWCAP_MTE] = "mte",
  92. [KERNEL_HWCAP_ECV] = "ecv",
  93. [KERNEL_HWCAP_AFP] = "afp",
  94. [KERNEL_HWCAP_RPRES] = "rpres",
  95. };
  96. #ifdef CONFIG_COMPAT
  97. #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x)
  98. static const char *const compat_hwcap_str[] = {
  99. [COMPAT_KERNEL_HWCAP(SWP)] = "swp",
  100. [COMPAT_KERNEL_HWCAP(HALF)] = "half",
  101. [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb",
  102. [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */
  103. [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult",
  104. [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */
  105. [COMPAT_KERNEL_HWCAP(VFP)] = "vfp",
  106. [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp",
  107. [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */
  108. [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */
  109. [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */
  110. [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */
  111. [COMPAT_KERNEL_HWCAP(NEON)] = "neon",
  112. [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3",
  113. [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */
  114. [COMPAT_KERNEL_HWCAP(TLS)] = "tls",
  115. [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4",
  116. [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva",
  117. [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt",
  118. [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */
  119. [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae",
  120. [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm",
  121. };
  122. #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
  123. static const char *const compat_hwcap2_str[] = {
  124. [COMPAT_KERNEL_HWCAP2(AES)] = "aes",
  125. [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull",
  126. [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1",
  127. [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2",
  128. [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32",
  129. };
  130. #endif /* CONFIG_COMPAT */
  131. static int c_show(struct seq_file *m, void *v)
  132. {
  133. int i, j;
  134. bool compat = personality(current->personality) == PER_LINUX32;
  135. for_each_online_cpu(i) {
  136. struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
  137. u32 midr = cpuinfo->reg_midr;
  138. /*
  139. * glibc reads /proc/cpuinfo to determine the number of
  140. * online processors, looking for lines beginning with
  141. * "processor". Give glibc what it expects.
  142. */
  143. seq_printf(m, "processor\t: %d\n", i);
  144. if (compat)
  145. seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
  146. MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
  147. seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
  148. loops_per_jiffy / (500000UL/HZ),
  149. loops_per_jiffy / (5000UL/HZ) % 100);
  150. /*
  151. * Dump out the common processor features in a single line.
  152. * Userspace should read the hwcaps with getauxval(AT_HWCAP)
  153. * rather than attempting to parse this, but there's a body of
  154. * software which does already (at least for 32-bit).
  155. */
  156. seq_puts(m, "Features\t:");
  157. if (compat) {
  158. #ifdef CONFIG_COMPAT
  159. for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) {
  160. if (compat_elf_hwcap & (1 << j)) {
  161. /*
  162. * Warn once if any feature should not
  163. * have been present on arm64 platform.
  164. */
  165. if (WARN_ON_ONCE(!compat_hwcap_str[j]))
  166. continue;
  167. seq_printf(m, " %s", compat_hwcap_str[j]);
  168. }
  169. }
  170. for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++)
  171. if (compat_elf_hwcap2 & (1 << j))
  172. seq_printf(m, " %s", compat_hwcap2_str[j]);
  173. #endif /* CONFIG_COMPAT */
  174. } else {
  175. for (j = 0; j < ARRAY_SIZE(hwcap_str); j++)
  176. if (cpu_have_feature(j))
  177. seq_printf(m, " %s", hwcap_str[j]);
  178. }
  179. seq_puts(m, "\n");
  180. seq_printf(m, "CPU implementer\t: 0x%02x\n",
  181. MIDR_IMPLEMENTOR(midr));
  182. seq_printf(m, "CPU architecture: 8\n");
  183. seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
  184. seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
  185. seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
  186. }
  187. return 0;
  188. }
  189. static void *c_start(struct seq_file *m, loff_t *pos)
  190. {
  191. return *pos < 1 ? (void *)1 : NULL;
  192. }
  193. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  194. {
  195. ++*pos;
  196. return NULL;
  197. }
  198. static void c_stop(struct seq_file *m, void *v)
  199. {
  200. }
  201. const struct seq_operations cpuinfo_op = {
  202. .start = c_start,
  203. .next = c_next,
  204. .stop = c_stop,
  205. .show = c_show
  206. };
  207. static struct kobj_type cpuregs_kobj_type = {
  208. .sysfs_ops = &kobj_sysfs_ops,
  209. };
  210. /*
  211. * The ARM ARM uses the phrase "32-bit register" to describe a register
  212. * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
  213. * no statement is made as to whether the upper 32 bits will or will not
  214. * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
  215. * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
  216. *
  217. * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
  218. * registers, we expose them both as 64 bit values to cater for possible
  219. * future expansion without an ABI break.
  220. */
  221. #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj)
  222. #define CPUREGS_ATTR_RO(_name, _field) \
  223. static ssize_t _name##_show(struct kobject *kobj, \
  224. struct kobj_attribute *attr, char *buf) \
  225. { \
  226. struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
  227. \
  228. if (info->reg_midr) \
  229. return sprintf(buf, "0x%016x\n", info->reg_##_field); \
  230. else \
  231. return 0; \
  232. } \
  233. static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
  234. CPUREGS_ATTR_RO(midr_el1, midr);
  235. CPUREGS_ATTR_RO(revidr_el1, revidr);
  236. static struct attribute *cpuregs_id_attrs[] = {
  237. &cpuregs_attr_midr_el1.attr,
  238. &cpuregs_attr_revidr_el1.attr,
  239. NULL
  240. };
  241. static const struct attribute_group cpuregs_attr_group = {
  242. .attrs = cpuregs_id_attrs,
  243. .name = "identification"
  244. };
  245. static int cpuid_cpu_online(unsigned int cpu)
  246. {
  247. int rc;
  248. struct device *dev;
  249. struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
  250. dev = get_cpu_device(cpu);
  251. if (!dev) {
  252. rc = -ENODEV;
  253. goto out;
  254. }
  255. rc = kobject_add(&info->kobj, &dev->kobj, "regs");
  256. if (rc)
  257. goto out;
  258. rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
  259. if (rc)
  260. kobject_del(&info->kobj);
  261. out:
  262. return rc;
  263. }
  264. static int cpuid_cpu_offline(unsigned int cpu)
  265. {
  266. struct device *dev;
  267. struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
  268. dev = get_cpu_device(cpu);
  269. if (!dev)
  270. return -ENODEV;
  271. if (info->kobj.parent) {
  272. sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
  273. kobject_del(&info->kobj);
  274. }
  275. return 0;
  276. }
  277. static int __init cpuinfo_regs_init(void)
  278. {
  279. int cpu, ret;
  280. for_each_possible_cpu(cpu) {
  281. struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
  282. kobject_init(&info->kobj, &cpuregs_kobj_type);
  283. }
  284. ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
  285. cpuid_cpu_online, cpuid_cpu_offline);
  286. if (ret < 0) {
  287. pr_err("cpuinfo: failed to register hotplug callbacks.\n");
  288. return ret;
  289. }
  290. return 0;
  291. }
  292. device_initcall(cpuinfo_regs_init);
  293. static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
  294. {
  295. unsigned int cpu = smp_processor_id();
  296. u32 l1ip = CTR_L1IP(info->reg_ctr);
  297. switch (l1ip) {
  298. case ICACHE_POLICY_PIPT:
  299. break;
  300. case ICACHE_POLICY_VPIPT:
  301. set_bit(ICACHEF_VPIPT, &__icache_flags);
  302. break;
  303. case ICACHE_POLICY_RESERVED:
  304. case ICACHE_POLICY_VIPT:
  305. /* Assume aliasing */
  306. set_bit(ICACHEF_ALIASING, &__icache_flags);
  307. break;
  308. }
  309. pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
  310. }
  311. static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)
  312. {
  313. info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
  314. info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);
  315. info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
  316. info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
  317. info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
  318. info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
  319. info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
  320. info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
  321. info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);
  322. info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
  323. info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
  324. info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
  325. info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
  326. info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
  327. info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
  328. info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
  329. info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
  330. info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);
  331. info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
  332. info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
  333. info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
  334. }
  335. static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
  336. {
  337. info->reg_cntfrq = arch_timer_get_cntfrq();
  338. /*
  339. * Use the effective value of the CTR_EL0 than the raw value
  340. * exposed by the CPU. CTR_EL0.IDC field value must be interpreted
  341. * with the CLIDR_EL1 fields to avoid triggering false warnings
  342. * when there is a mismatch across the CPUs. Keep track of the
  343. * effective value of the CTR_EL0 in our internal records for
  344. * acurate sanity check and feature enablement.
  345. */
  346. info->reg_ctr = read_cpuid_effective_cachetype();
  347. info->reg_dczid = read_cpuid(DCZID_EL0);
  348. info->reg_midr = read_cpuid_id();
  349. info->reg_revidr = read_cpuid(REVIDR_EL1);
  350. info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
  351. info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
  352. info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
  353. info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
  354. info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
  355. info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
  356. info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
  357. info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
  358. info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
  359. info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
  360. info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
  361. if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
  362. __cpuinfo_store_cpu_32bit(&info->aarch32);
  363. if (IS_ENABLED(CONFIG_ARM64_SVE) &&
  364. id_aa64pfr0_sve(info->reg_id_aa64pfr0))
  365. info->reg_zcr = read_zcr_features();
  366. cpuinfo_detect_icache_policy(info);
  367. }
  368. void cpuinfo_store_cpu(void)
  369. {
  370. struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
  371. __cpuinfo_store_cpu(info);
  372. update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
  373. }
  374. void __init cpuinfo_store_boot_cpu(void)
  375. {
  376. struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
  377. __cpuinfo_store_cpu(info);
  378. boot_cpu_data = *info;
  379. init_cpu_features(&boot_cpu_data);
  380. }