armv8_deprecated.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2014 ARM Limited
  4. */
  5. #include <linux/cpu.h>
  6. #include <linux/init.h>
  7. #include <linux/list.h>
  8. #include <linux/perf_event.h>
  9. #include <linux/sched.h>
  10. #include <linux/slab.h>
  11. #include <linux/sysctl.h>
  12. #include <linux/uaccess.h>
  13. #include <asm/cpufeature.h>
  14. #include <asm/insn.h>
  15. #include <asm/sysreg.h>
  16. #include <asm/system_misc.h>
  17. #include <asm/traps.h>
  18. #include <asm/kprobes.h>
  19. #define CREATE_TRACE_POINTS
  20. #include "trace-events-emulation.h"
  21. /*
  22. * The runtime support for deprecated instruction support can be in one of
  23. * following three states -
  24. *
  25. * 0 = undef
  26. * 1 = emulate (software emulation)
  27. * 2 = hw (supported in hardware)
  28. */
  29. enum insn_emulation_mode {
  30. INSN_UNDEF,
  31. INSN_EMULATE,
  32. INSN_HW,
  33. };
  34. enum legacy_insn_status {
  35. INSN_DEPRECATED,
  36. INSN_OBSOLETE,
  37. };
  38. struct insn_emulation_ops {
  39. const char *name;
  40. enum legacy_insn_status status;
  41. struct undef_hook *hooks;
  42. int (*set_hw_mode)(bool enable);
  43. };
  44. struct insn_emulation {
  45. struct list_head node;
  46. struct insn_emulation_ops *ops;
  47. int current_mode;
  48. int min;
  49. int max;
  50. };
  51. static LIST_HEAD(insn_emulation);
  52. static int nr_insn_emulated __initdata;
  53. static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
  54. static void register_emulation_hooks(struct insn_emulation_ops *ops)
  55. {
  56. struct undef_hook *hook;
  57. BUG_ON(!ops->hooks);
  58. for (hook = ops->hooks; hook->instr_mask; hook++)
  59. register_undef_hook(hook);
  60. pr_notice("Registered %s emulation handler\n", ops->name);
  61. }
  62. static void remove_emulation_hooks(struct insn_emulation_ops *ops)
  63. {
  64. struct undef_hook *hook;
  65. BUG_ON(!ops->hooks);
  66. for (hook = ops->hooks; hook->instr_mask; hook++)
  67. unregister_undef_hook(hook);
  68. pr_notice("Removed %s emulation handler\n", ops->name);
  69. }
  70. static void enable_insn_hw_mode(void *data)
  71. {
  72. struct insn_emulation *insn = (struct insn_emulation *)data;
  73. if (insn->ops->set_hw_mode)
  74. insn->ops->set_hw_mode(true);
  75. }
  76. static void disable_insn_hw_mode(void *data)
  77. {
  78. struct insn_emulation *insn = (struct insn_emulation *)data;
  79. if (insn->ops->set_hw_mode)
  80. insn->ops->set_hw_mode(false);
  81. }
  82. /* Run set_hw_mode(mode) on all active CPUs */
  83. static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
  84. {
  85. if (!insn->ops->set_hw_mode)
  86. return -EINVAL;
  87. if (enable)
  88. on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
  89. else
  90. on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
  91. return 0;
  92. }
  93. /*
  94. * Run set_hw_mode for all insns on a starting CPU.
  95. * Returns:
  96. * 0 - If all the hooks ran successfully.
  97. * -EINVAL - At least one hook is not supported by the CPU.
  98. */
  99. static int run_all_insn_set_hw_mode(unsigned int cpu)
  100. {
  101. int rc = 0;
  102. unsigned long flags;
  103. struct insn_emulation *insn;
  104. raw_spin_lock_irqsave(&insn_emulation_lock, flags);
  105. list_for_each_entry(insn, &insn_emulation, node) {
  106. bool enable = (insn->current_mode == INSN_HW);
  107. if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
  108. pr_warn("CPU[%u] cannot support the emulation of %s",
  109. cpu, insn->ops->name);
  110. rc = -EINVAL;
  111. }
  112. }
  113. raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
  114. return rc;
  115. }
  116. static int update_insn_emulation_mode(struct insn_emulation *insn,
  117. enum insn_emulation_mode prev)
  118. {
  119. int ret = 0;
  120. switch (prev) {
  121. case INSN_UNDEF: /* Nothing to be done */
  122. break;
  123. case INSN_EMULATE:
  124. remove_emulation_hooks(insn->ops);
  125. break;
  126. case INSN_HW:
  127. if (!run_all_cpu_set_hw_mode(insn, false))
  128. pr_notice("Disabled %s support\n", insn->ops->name);
  129. break;
  130. }
  131. switch (insn->current_mode) {
  132. case INSN_UNDEF:
  133. break;
  134. case INSN_EMULATE:
  135. register_emulation_hooks(insn->ops);
  136. break;
  137. case INSN_HW:
  138. ret = run_all_cpu_set_hw_mode(insn, true);
  139. if (!ret)
  140. pr_notice("Enabled %s support\n", insn->ops->name);
  141. break;
  142. }
  143. return ret;
  144. }
  145. static void __init register_insn_emulation(struct insn_emulation_ops *ops)
  146. {
  147. unsigned long flags;
  148. struct insn_emulation *insn;
  149. insn = kzalloc(sizeof(*insn), GFP_KERNEL);
  150. if (!insn)
  151. return;
  152. insn->ops = ops;
  153. insn->min = INSN_UNDEF;
  154. switch (ops->status) {
  155. case INSN_DEPRECATED:
  156. insn->current_mode = INSN_EMULATE;
  157. /* Disable the HW mode if it was turned on at early boot time */
  158. run_all_cpu_set_hw_mode(insn, false);
  159. insn->max = INSN_HW;
  160. break;
  161. case INSN_OBSOLETE:
  162. insn->current_mode = INSN_UNDEF;
  163. insn->max = INSN_EMULATE;
  164. break;
  165. }
  166. raw_spin_lock_irqsave(&insn_emulation_lock, flags);
  167. list_add(&insn->node, &insn_emulation);
  168. nr_insn_emulated++;
  169. raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
  170. /* Register any handlers if required */
  171. update_insn_emulation_mode(insn, INSN_UNDEF);
  172. }
  173. static int emulation_proc_handler(struct ctl_table *table, int write,
  174. void *buffer, size_t *lenp,
  175. loff_t *ppos)
  176. {
  177. int ret = 0;
  178. struct insn_emulation *insn = (struct insn_emulation *) table->data;
  179. enum insn_emulation_mode prev_mode = insn->current_mode;
  180. table->data = &insn->current_mode;
  181. ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
  182. if (ret || !write || prev_mode == insn->current_mode)
  183. goto ret;
  184. ret = update_insn_emulation_mode(insn, prev_mode);
  185. if (ret) {
  186. /* Mode change failed, revert to previous mode. */
  187. insn->current_mode = prev_mode;
  188. update_insn_emulation_mode(insn, INSN_UNDEF);
  189. }
  190. ret:
  191. table->data = insn;
  192. return ret;
  193. }
  194. static void __init register_insn_emulation_sysctl(void)
  195. {
  196. unsigned long flags;
  197. int i = 0;
  198. struct insn_emulation *insn;
  199. struct ctl_table *insns_sysctl, *sysctl;
  200. insns_sysctl = kcalloc(nr_insn_emulated + 1, sizeof(*sysctl),
  201. GFP_KERNEL);
  202. if (!insns_sysctl)
  203. return;
  204. raw_spin_lock_irqsave(&insn_emulation_lock, flags);
  205. list_for_each_entry(insn, &insn_emulation, node) {
  206. sysctl = &insns_sysctl[i];
  207. sysctl->mode = 0644;
  208. sysctl->maxlen = sizeof(int);
  209. sysctl->procname = insn->ops->name;
  210. sysctl->data = insn;
  211. sysctl->extra1 = &insn->min;
  212. sysctl->extra2 = &insn->max;
  213. sysctl->proc_handler = emulation_proc_handler;
  214. i++;
  215. }
  216. raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
  217. register_sysctl("abi", insns_sysctl);
  218. }
  219. /*
  220. * Implement emulation of the SWP/SWPB instructions using load-exclusive and
  221. * store-exclusive.
  222. *
  223. * Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
  224. * Where: Rt = destination
  225. * Rt2 = source
  226. * Rn = address
  227. */
  228. /*
  229. * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
  230. */
  231. /* Arbitrary constant to ensure forward-progress of the LL/SC loop */
  232. #define __SWP_LL_SC_LOOPS 4
  233. #define __user_swpX_asm(data, addr, res, temp, temp2, B) \
  234. do { \
  235. uaccess_enable_privileged(); \
  236. __asm__ __volatile__( \
  237. " mov %w3, %w7\n" \
  238. "0: ldxr"B" %w2, [%4]\n" \
  239. "1: stxr"B" %w0, %w1, [%4]\n" \
  240. " cbz %w0, 2f\n" \
  241. " sub %w3, %w3, #1\n" \
  242. " cbnz %w3, 0b\n" \
  243. " mov %w0, %w5\n" \
  244. " b 3f\n" \
  245. "2:\n" \
  246. " mov %w1, %w2\n" \
  247. "3:\n" \
  248. " .pushsection .fixup,\"ax\"\n" \
  249. " .align 2\n" \
  250. "4: mov %w0, %w6\n" \
  251. " b 3b\n" \
  252. " .popsection" \
  253. _ASM_EXTABLE(0b, 4b) \
  254. _ASM_EXTABLE(1b, 4b) \
  255. : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
  256. : "r" ((unsigned long)addr), "i" (-EAGAIN), \
  257. "i" (-EFAULT), \
  258. "i" (__SWP_LL_SC_LOOPS) \
  259. : "memory"); \
  260. uaccess_disable_privileged(); \
  261. } while (0)
  262. #define __user_swp_asm(data, addr, res, temp, temp2) \
  263. __user_swpX_asm(data, addr, res, temp, temp2, "")
  264. #define __user_swpb_asm(data, addr, res, temp, temp2) \
  265. __user_swpX_asm(data, addr, res, temp, temp2, "b")
  266. /*
  267. * Bit 22 of the instruction encoding distinguishes between
  268. * the SWP and SWPB variants (bit set means SWPB).
  269. */
  270. #define TYPE_SWPB (1 << 22)
  271. static int emulate_swpX(unsigned int address, unsigned int *data,
  272. unsigned int type)
  273. {
  274. unsigned int res = 0;
  275. if ((type != TYPE_SWPB) && (address & 0x3)) {
  276. /* SWP to unaligned address not permitted */
  277. pr_debug("SWP instruction on unaligned pointer!\n");
  278. return -EFAULT;
  279. }
  280. while (1) {
  281. unsigned long temp, temp2;
  282. if (type == TYPE_SWPB)
  283. __user_swpb_asm(*data, address, res, temp, temp2);
  284. else
  285. __user_swp_asm(*data, address, res, temp, temp2);
  286. if (likely(res != -EAGAIN) || signal_pending(current))
  287. break;
  288. cond_resched();
  289. }
  290. return res;
  291. }
  292. #define ARM_OPCODE_CONDTEST_FAIL 0
  293. #define ARM_OPCODE_CONDTEST_PASS 1
  294. #define ARM_OPCODE_CONDTEST_UNCOND 2
  295. #define ARM_OPCODE_CONDITION_UNCOND 0xf
  296. static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
  297. {
  298. u32 cc_bits = opcode >> 28;
  299. if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
  300. if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
  301. return ARM_OPCODE_CONDTEST_PASS;
  302. else
  303. return ARM_OPCODE_CONDTEST_FAIL;
  304. }
  305. return ARM_OPCODE_CONDTEST_UNCOND;
  306. }
  307. /*
  308. * swp_handler logs the id of calling process, dissects the instruction, sanity
  309. * checks the memory location, calls emulate_swpX for the actual operation and
  310. * deals with fixup/error handling before returning
  311. */
  312. static int swp_handler(struct pt_regs *regs, u32 instr)
  313. {
  314. u32 destreg, data, type, address = 0;
  315. const void __user *user_ptr;
  316. int rn, rt2, res = 0;
  317. perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
  318. type = instr & TYPE_SWPB;
  319. switch (aarch32_check_condition(instr, regs->pstate)) {
  320. case ARM_OPCODE_CONDTEST_PASS:
  321. break;
  322. case ARM_OPCODE_CONDTEST_FAIL:
  323. /* Condition failed - return to next instruction */
  324. goto ret;
  325. case ARM_OPCODE_CONDTEST_UNCOND:
  326. /* If unconditional encoding - not a SWP, undef */
  327. return -EFAULT;
  328. default:
  329. return -EINVAL;
  330. }
  331. rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
  332. rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
  333. address = (u32)regs->user_regs.regs[rn];
  334. data = (u32)regs->user_regs.regs[rt2];
  335. destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
  336. pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
  337. rn, address, destreg,
  338. aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
  339. /* Check access in reasonable access range for both SWP and SWPB */
  340. user_ptr = (const void __user *)(unsigned long)(address & ~3);
  341. if (!access_ok(user_ptr, 4)) {
  342. pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
  343. address);
  344. goto fault;
  345. }
  346. res = emulate_swpX(address, &data, type);
  347. if (res == -EFAULT)
  348. goto fault;
  349. else if (res == 0)
  350. regs->user_regs.regs[destreg] = data;
  351. ret:
  352. if (type == TYPE_SWPB)
  353. trace_instruction_emulation("swpb", regs->pc);
  354. else
  355. trace_instruction_emulation("swp", regs->pc);
  356. pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
  357. current->comm, (unsigned long)current->pid, regs->pc);
  358. arm64_skip_faulting_instruction(regs, 4);
  359. return 0;
  360. fault:
  361. pr_debug("SWP{B} emulation: access caused memory abort!\n");
  362. arm64_notify_segfault(address);
  363. return 0;
  364. }
  365. /*
  366. * Only emulate SWP/SWPB executed in ARM state/User mode.
  367. * The kernel must be SWP free and SWP{B} does not exist in Thumb.
  368. */
  369. static struct undef_hook swp_hooks[] = {
  370. {
  371. .instr_mask = 0x0fb00ff0,
  372. .instr_val = 0x01000090,
  373. .pstate_mask = PSR_AA32_MODE_MASK,
  374. .pstate_val = PSR_AA32_MODE_USR,
  375. .fn = swp_handler
  376. },
  377. { }
  378. };
  379. static struct insn_emulation_ops swp_ops = {
  380. .name = "swp",
  381. .status = INSN_OBSOLETE,
  382. .hooks = swp_hooks,
  383. .set_hw_mode = NULL,
  384. };
  385. static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
  386. {
  387. perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
  388. switch (aarch32_check_condition(instr, regs->pstate)) {
  389. case ARM_OPCODE_CONDTEST_PASS:
  390. break;
  391. case ARM_OPCODE_CONDTEST_FAIL:
  392. /* Condition failed - return to next instruction */
  393. goto ret;
  394. case ARM_OPCODE_CONDTEST_UNCOND:
  395. /* If unconditional encoding - not a barrier instruction */
  396. return -EFAULT;
  397. default:
  398. return -EINVAL;
  399. }
  400. switch (aarch32_insn_mcr_extract_crm(instr)) {
  401. case 10:
  402. /*
  403. * dmb - mcr p15, 0, Rt, c7, c10, 5
  404. * dsb - mcr p15, 0, Rt, c7, c10, 4
  405. */
  406. if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
  407. dmb(sy);
  408. trace_instruction_emulation(
  409. "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
  410. } else {
  411. dsb(sy);
  412. trace_instruction_emulation(
  413. "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
  414. }
  415. break;
  416. case 5:
  417. /*
  418. * isb - mcr p15, 0, Rt, c7, c5, 4
  419. *
  420. * Taking an exception or returning from one acts as an
  421. * instruction barrier. So no explicit barrier needed here.
  422. */
  423. trace_instruction_emulation(
  424. "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
  425. break;
  426. }
  427. ret:
  428. pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
  429. current->comm, (unsigned long)current->pid, regs->pc);
  430. arm64_skip_faulting_instruction(regs, 4);
  431. return 0;
  432. }
  433. static int cp15_barrier_set_hw_mode(bool enable)
  434. {
  435. if (enable)
  436. sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_CP15BEN);
  437. else
  438. sysreg_clear_set(sctlr_el1, SCTLR_EL1_CP15BEN, 0);
  439. return 0;
  440. }
  441. static struct undef_hook cp15_barrier_hooks[] = {
  442. {
  443. .instr_mask = 0x0fff0fdf,
  444. .instr_val = 0x0e070f9a,
  445. .pstate_mask = PSR_AA32_MODE_MASK,
  446. .pstate_val = PSR_AA32_MODE_USR,
  447. .fn = cp15barrier_handler,
  448. },
  449. {
  450. .instr_mask = 0x0fff0fff,
  451. .instr_val = 0x0e070f95,
  452. .pstate_mask = PSR_AA32_MODE_MASK,
  453. .pstate_val = PSR_AA32_MODE_USR,
  454. .fn = cp15barrier_handler,
  455. },
  456. { }
  457. };
  458. static struct insn_emulation_ops cp15_barrier_ops = {
  459. .name = "cp15_barrier",
  460. .status = INSN_DEPRECATED,
  461. .hooks = cp15_barrier_hooks,
  462. .set_hw_mode = cp15_barrier_set_hw_mode,
  463. };
  464. static int setend_set_hw_mode(bool enable)
  465. {
  466. if (!cpu_supports_mixed_endian_el0())
  467. return -EINVAL;
  468. if (enable)
  469. sysreg_clear_set(sctlr_el1, SCTLR_EL1_SED, 0);
  470. else
  471. sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_SED);
  472. return 0;
  473. }
  474. static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
  475. {
  476. char *insn;
  477. perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
  478. if (big_endian) {
  479. insn = "setend be";
  480. regs->pstate |= PSR_AA32_E_BIT;
  481. } else {
  482. insn = "setend le";
  483. regs->pstate &= ~PSR_AA32_E_BIT;
  484. }
  485. trace_instruction_emulation(insn, regs->pc);
  486. pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
  487. current->comm, (unsigned long)current->pid, regs->pc);
  488. return 0;
  489. }
  490. static int a32_setend_handler(struct pt_regs *regs, u32 instr)
  491. {
  492. int rc = compat_setend_handler(regs, (instr >> 9) & 1);
  493. arm64_skip_faulting_instruction(regs, 4);
  494. return rc;
  495. }
  496. static int t16_setend_handler(struct pt_regs *regs, u32 instr)
  497. {
  498. int rc = compat_setend_handler(regs, (instr >> 3) & 1);
  499. arm64_skip_faulting_instruction(regs, 2);
  500. return rc;
  501. }
  502. static struct undef_hook setend_hooks[] = {
  503. {
  504. .instr_mask = 0xfffffdff,
  505. .instr_val = 0xf1010000,
  506. .pstate_mask = PSR_AA32_MODE_MASK,
  507. .pstate_val = PSR_AA32_MODE_USR,
  508. .fn = a32_setend_handler,
  509. },
  510. {
  511. /* Thumb mode */
  512. .instr_mask = 0xfffffff7,
  513. .instr_val = 0x0000b650,
  514. .pstate_mask = (PSR_AA32_T_BIT | PSR_AA32_MODE_MASK),
  515. .pstate_val = (PSR_AA32_T_BIT | PSR_AA32_MODE_USR),
  516. .fn = t16_setend_handler,
  517. },
  518. {}
  519. };
  520. static struct insn_emulation_ops setend_ops = {
  521. .name = "setend",
  522. .status = INSN_DEPRECATED,
  523. .hooks = setend_hooks,
  524. .set_hw_mode = setend_set_hw_mode,
  525. };
  526. /*
  527. * Invoked as core_initcall, which guarantees that the instruction
  528. * emulation is ready for userspace.
  529. */
  530. static int __init armv8_deprecated_init(void)
  531. {
  532. if (IS_ENABLED(CONFIG_SWP_EMULATION))
  533. register_insn_emulation(&swp_ops);
  534. if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
  535. register_insn_emulation(&cp15_barrier_ops);
  536. if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
  537. if (system_supports_mixed_endian_el0())
  538. register_insn_emulation(&setend_ops);
  539. else
  540. pr_info("setend instruction emulation is not supported on this system\n");
  541. }
  542. cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
  543. "arm64/isndep:starting",
  544. run_all_insn_set_hw_mode, NULL);
  545. register_insn_emulation_sysctl();
  546. return 0;
  547. }
  548. core_initcall(armv8_deprecated_init);