counter_32k.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * OMAP 32ksynctimer/counter_32k-related code
  4. *
  5. * Copyright (C) 2009 Texas Instruments
  6. * Copyright (C) 2010 Nokia Corporation
  7. * Tony Lindgren <tony@atomide.com>
  8. * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  9. *
  10. * NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/clk.h>
  15. #include <linux/err.h>
  16. #include <linux/io.h>
  17. #include <linux/clocksource.h>
  18. #include <linux/sched_clock.h>
  19. #include <asm/mach/time.h>
  20. #include <plat/counter-32k.h>
  21. /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
  22. #define OMAP2_32KSYNCNT_REV_OFF 0x0
  23. #define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
  24. #define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
  25. #define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
  26. /*
  27. * 32KHz clocksource ... always available, on pretty most chips except
  28. * OMAP 730 and 1510. Other timers could be used as clocksources, with
  29. * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
  30. * but systems won't necessarily want to spend resources that way.
  31. */
  32. static void __iomem *sync32k_cnt_reg;
  33. static u64 notrace omap_32k_read_sched_clock(void)
  34. {
  35. return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
  36. }
  37. /**
  38. * omap_read_persistent_clock64 - Return time from a persistent clock.
  39. *
  40. * Reads the time from a source which isn't disabled during PM, the
  41. * 32k sync timer. Convert the cycles elapsed since last read into
  42. * nsecs and adds to a monotonically increasing timespec64.
  43. */
  44. static struct timespec64 persistent_ts;
  45. static cycles_t cycles;
  46. static unsigned int persistent_mult, persistent_shift;
  47. static void omap_read_persistent_clock64(struct timespec64 *ts)
  48. {
  49. unsigned long long nsecs;
  50. cycles_t last_cycles;
  51. last_cycles = cycles;
  52. cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
  53. nsecs = clocksource_cyc2ns(cycles - last_cycles,
  54. persistent_mult, persistent_shift);
  55. timespec64_add_ns(&persistent_ts, nsecs);
  56. *ts = persistent_ts;
  57. }
  58. /**
  59. * omap_init_clocksource_32k - setup and register counter 32k as a
  60. * kernel clocksource
  61. * @pbase: base addr of counter_32k module
  62. * @size: size of counter_32k to map
  63. *
  64. * Returns 0 upon success or negative error code upon failure.
  65. *
  66. */
  67. int __init omap_init_clocksource_32k(void __iomem *vbase)
  68. {
  69. int ret;
  70. /*
  71. * 32k sync Counter IP register offsets vary between the
  72. * highlander version and the legacy ones.
  73. * The 'SCHEME' bits(30-31) of the revision register is used
  74. * to identify the version.
  75. */
  76. if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) &
  77. OMAP2_32KSYNCNT_REV_SCHEME)
  78. sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
  79. else
  80. sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
  81. /*
  82. * 120000 rough estimate from the calculations in
  83. * __clocksource_update_freq_scale.
  84. */
  85. clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
  86. 32768, NSEC_PER_SEC, 120000);
  87. ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
  88. 250, 32, clocksource_mmio_readl_up);
  89. if (ret) {
  90. pr_err("32k_counter: can't register clocksource\n");
  91. return ret;
  92. }
  93. sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
  94. register_persistent_clock(omap_read_persistent_clock64);
  95. pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
  96. return 0;
  97. }