fpsr.h 3.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. NetWinder Floating Point Emulator
  4. (c) Rebel.com, 1998-1999
  5. Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
  6. */
  7. #ifndef __FPSR_H__
  8. #define __FPSR_H__
  9. /*
  10. The FPSR is a 32 bit register consisting of 4 parts, each exactly
  11. one byte.
  12. SYSTEM ID
  13. EXCEPTION TRAP ENABLE BYTE
  14. SYSTEM CONTROL BYTE
  15. CUMULATIVE EXCEPTION FLAGS BYTE
  16. The FPCR is a 32 bit register consisting of bit flags.
  17. */
  18. /* SYSTEM ID
  19. ------------
  20. Note: the system id byte is read only */
  21. typedef unsigned int FPSR; /* type for floating point status register */
  22. typedef unsigned int FPCR; /* type for floating point control register */
  23. #define MASK_SYSID 0xff000000
  24. #define BIT_HARDWARE 0x80000000
  25. #define FP_EMULATOR 0x01000000 /* System ID for emulator */
  26. #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */
  27. /* EXCEPTION TRAP ENABLE BYTE
  28. ----------------------------- */
  29. #define MASK_TRAP_ENABLE 0x00ff0000
  30. #define MASK_TRAP_ENABLE_STRICT 0x001f0000
  31. #define BIT_IXE 0x00100000 /* inexact exception enable */
  32. #define BIT_UFE 0x00080000 /* underflow exception enable */
  33. #define BIT_OFE 0x00040000 /* overflow exception enable */
  34. #define BIT_DZE 0x00020000 /* divide by zero exception enable */
  35. #define BIT_IOE 0x00010000 /* invalid operation exception enable */
  36. /* SYSTEM CONTROL BYTE
  37. ---------------------- */
  38. #define MASK_SYSTEM_CONTROL 0x0000ff00
  39. #define MASK_TRAP_STRICT 0x00001f00
  40. #define BIT_AC 0x00001000 /* use alternative C-flag definition
  41. for compares */
  42. #define BIT_EP 0x00000800 /* use expanded packed decimal format */
  43. #define BIT_SO 0x00000400 /* select synchronous operation of FPA */
  44. #define BIT_NE 0x00000200 /* NaN exception bit */
  45. #define BIT_ND 0x00000100 /* no denormalized numbers bit */
  46. /* CUMULATIVE EXCEPTION FLAGS BYTE
  47. ---------------------------------- */
  48. #define MASK_EXCEPTION_FLAGS 0x000000ff
  49. #define MASK_EXCEPTION_FLAGS_STRICT 0x0000001f
  50. #define BIT_IXC 0x00000010 /* inexact exception flag */
  51. #define BIT_UFC 0x00000008 /* underflow exception flag */
  52. #define BIT_OFC 0x00000004 /* overfloat exception flag */
  53. #define BIT_DZC 0x00000002 /* divide by zero exception flag */
  54. #define BIT_IOC 0x00000001 /* invalid operation exception flag */
  55. /* Floating Point Control Register
  56. ----------------------------------*/
  57. #define BIT_RU 0x80000000 /* rounded up bit */
  58. #define BIT_IE 0x10000000 /* inexact bit */
  59. #define BIT_MO 0x08000000 /* mantissa overflow bit */
  60. #define BIT_EO 0x04000000 /* exponent overflow bit */
  61. #define BIT_SB 0x00000800 /* store bounce */
  62. #define BIT_AB 0x00000400 /* arithmetic bounce */
  63. #define BIT_RE 0x00000200 /* rounding exception */
  64. #define BIT_DA 0x00000100 /* disable FPA */
  65. #define MASK_OP 0x00f08010 /* AU operation code */
  66. #define MASK_PR 0x00080080 /* AU precision */
  67. #define MASK_S1 0x00070000 /* AU source register 1 */
  68. #define MASK_S2 0x00000007 /* AU source register 2 */
  69. #define MASK_DS 0x00007000 /* AU destination register */
  70. #define MASK_RM 0x00000060 /* AU rounding mode */
  71. #define MASK_ALU 0x9cfff2ff /* only ALU can write these bits */
  72. #define MASK_RESET 0x00000d00 /* bits set on reset, all others cleared */
  73. #define MASK_WFC MASK_RESET
  74. #define MASK_RFC ~MASK_RESET
  75. #endif