platsmp.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2002 ARM Ltd.
  4. * Copyright (C) 2008 STMicroelctronics.
  5. * Copyright (C) 2009 ST-Ericsson.
  6. * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
  7. *
  8. * This file is based on arm realview platform
  9. */
  10. #include <linux/init.h>
  11. #include <linux/errno.h>
  12. #include <linux/delay.h>
  13. #include <linux/device.h>
  14. #include <linux/smp.h>
  15. #include <linux/io.h>
  16. #include <linux/of.h>
  17. #include <linux/of_address.h>
  18. #include <asm/cacheflush.h>
  19. #include <asm/smp_plat.h>
  20. #include <asm/smp_scu.h>
  21. #include "db8500-regs.h"
  22. /* Magic triggers in backup RAM */
  23. #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
  24. #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
  25. static void __iomem *backupram;
  26. static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
  27. {
  28. struct device_node *np;
  29. static void __iomem *scu_base;
  30. unsigned int ncores;
  31. int i;
  32. np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram");
  33. if (!np) {
  34. pr_err("No backupram base address\n");
  35. return;
  36. }
  37. backupram = of_iomap(np, 0);
  38. of_node_put(np);
  39. if (!backupram) {
  40. pr_err("No backupram remap\n");
  41. return;
  42. }
  43. np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
  44. if (!np) {
  45. pr_err("No SCU base address\n");
  46. return;
  47. }
  48. scu_base = of_iomap(np, 0);
  49. of_node_put(np);
  50. if (!scu_base) {
  51. pr_err("No SCU remap\n");
  52. return;
  53. }
  54. scu_enable(scu_base);
  55. ncores = scu_get_core_count(scu_base);
  56. for (i = 0; i < ncores; i++)
  57. set_cpu_possible(i, true);
  58. iounmap(scu_base);
  59. }
  60. static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
  61. {
  62. /*
  63. * write the address of secondary startup into the backup ram register
  64. * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
  65. * backup ram register at offset 0x1FF0, which is what boot rom code
  66. * is waiting for. This will wake up the secondary core from WFE.
  67. */
  68. writel(__pa_symbol(secondary_startup),
  69. backupram + UX500_CPU1_JUMPADDR_OFFSET);
  70. writel(0xA1FEED01,
  71. backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
  72. /* make sure write buffer is drained */
  73. mb();
  74. arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  75. return 0;
  76. }
  77. #ifdef CONFIG_HOTPLUG_CPU
  78. void ux500_cpu_die(unsigned int cpu)
  79. {
  80. wfi();
  81. }
  82. #endif
  83. static const struct smp_operations ux500_smp_ops __initconst = {
  84. .smp_prepare_cpus = ux500_smp_prepare_cpus,
  85. .smp_boot_secondary = ux500_boot_secondary,
  86. #ifdef CONFIG_HOTPLUG_CPU
  87. .cpu_die = ux500_cpu_die,
  88. #endif
  89. };
  90. CPU_METHOD_OF_DECLARE(ux500_smp, "ste,dbx500-smp", &ux500_smp_ops);