core.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * arch/arm/mach-u300/core.c
  5. *
  6. * Copyright (C) 2007-2012 ST-Ericsson SA
  7. * Core platform support, IRQ handling and device definitions.
  8. * Author: Linus Walleij <linus.walleij@stericsson.com>
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/pinctrl/machine.h>
  12. #include <linux/pinctrl/pinconf-generic.h>
  13. #include <linux/platform_data/clk-u300.h>
  14. #include <linux/irqchip.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/clocksource.h>
  18. #include <linux/clk.h>
  19. #include <asm/mach/map.h>
  20. #include <asm/mach/arch.h>
  21. /*
  22. * These are the large blocks of memory allocated for I/O.
  23. * the defines are used for setting up the I/O memory mapping.
  24. */
  25. /* NAND Flash CS0 */
  26. #define U300_NAND_CS0_PHYS_BASE 0x80000000
  27. /* NFIF */
  28. #define U300_NAND_IF_PHYS_BASE 0x9f800000
  29. /* ALE, CLE offset for FSMC NAND */
  30. #define PLAT_NAND_CLE (1 << 16)
  31. #define PLAT_NAND_ALE (1 << 17)
  32. /* AHB Peripherals */
  33. #define U300_AHB_PER_PHYS_BASE 0xa0000000
  34. #define U300_AHB_PER_VIRT_BASE 0xff010000
  35. /* FAST Peripherals */
  36. #define U300_FAST_PER_PHYS_BASE 0xc0000000
  37. #define U300_FAST_PER_VIRT_BASE 0xff020000
  38. /* SLOW Peripherals */
  39. #define U300_SLOW_PER_PHYS_BASE 0xc0010000
  40. #define U300_SLOW_PER_VIRT_BASE 0xff000000
  41. /* Boot ROM */
  42. #define U300_BOOTROM_PHYS_BASE 0xffff0000
  43. #define U300_BOOTROM_VIRT_BASE 0xffff0000
  44. /* SEMI config base */
  45. #define U300_SEMI_CONFIG_BASE 0x2FFE0000
  46. /*
  47. * AHB peripherals
  48. */
  49. /* AHB Peripherals Bridge Controller */
  50. #define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
  51. /* Vectored Interrupt Controller 0, servicing 32 interrupts */
  52. #define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
  53. #define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
  54. /* Vectored Interrupt Controller 1, servicing 32 interrupts */
  55. #define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
  56. #define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
  57. /* Memory Stick Pro (MSPRO) controller */
  58. #define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
  59. /* EMIF Configuration Area */
  60. #define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
  61. /*
  62. * FAST peripherals
  63. */
  64. /* FAST bridge control */
  65. #define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
  66. /* MMC/SD controller */
  67. #define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
  68. /* PCM I2S0 controller */
  69. #define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
  70. /* PCM I2S1 controller */
  71. #define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
  72. /* I2C0 controller */
  73. #define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
  74. /* I2C1 controller */
  75. #define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
  76. /* SPI controller */
  77. #define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
  78. /* Fast UART1 on U335 only */
  79. #define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
  80. /*
  81. * SLOW peripherals
  82. */
  83. /* SLOW bridge control */
  84. #define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
  85. /* SYSCON */
  86. #define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
  87. #define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
  88. /* Watchdog */
  89. #define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
  90. /* UART0 */
  91. #define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
  92. /* APP side special timer */
  93. #define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
  94. #define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
  95. /* Keypad */
  96. #define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
  97. /* GPIO */
  98. #define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
  99. /* RTC */
  100. #define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
  101. /* Bus tracer */
  102. #define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
  103. /* Event handler (hardware queue) */
  104. #define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
  105. /* Genric Timer */
  106. #define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
  107. /* PPM */
  108. #define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
  109. /*
  110. * REST peripherals
  111. */
  112. /* ISP (image signal processor) */
  113. #define U300_ISP_BASE (0xA0008000)
  114. /* DMA Controller base */
  115. #define U300_DMAC_BASE (0xC0020000)
  116. /* MSL Base */
  117. #define U300_MSL_BASE (0xc0022000)
  118. /* APEX Base */
  119. #define U300_APEX_BASE (0xc0030000)
  120. /* Video Encoder Base */
  121. #define U300_VIDEOENC_BASE (0xc0080000)
  122. /* XGAM Base */
  123. #define U300_XGAM_BASE (0xd0000000)
  124. /*
  125. * SYSCON addresses applicable to the core machine.
  126. */
  127. /* Chip ID register 16bit (R/-) */
  128. #define U300_SYSCON_CIDR (0x400)
  129. /* SMCR */
  130. #define U300_SYSCON_SMCR (0x4d0)
  131. #define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
  132. #define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
  133. #define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
  134. #define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
  135. /* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
  136. #define U300_SYSCON_CSDR (0x4f0)
  137. #define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
  138. /* PRINT_CONTROL Print Control 16bit (R/-) */
  139. #define U300_SYSCON_PCR (0x4f8)
  140. #define U300_SYSCON_PCR_SERV_IND (0x0001)
  141. /* BOOT_CONTROL 16bit (R/-) */
  142. #define U300_SYSCON_BCR (0x4fc)
  143. #define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
  144. #define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
  145. #define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
  146. #define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
  147. static void __iomem *syscon_base;
  148. /*
  149. * Static I/O mappings that are needed for booting the U300 platforms. The
  150. * only things we need are the areas where we find the timer, syscon and
  151. * intcon, since the remaining device drivers will map their own memory
  152. * physical to virtual as the need arise.
  153. */
  154. static struct map_desc u300_io_desc[] __initdata = {
  155. {
  156. .virtual = U300_SLOW_PER_VIRT_BASE,
  157. .pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  158. .length = SZ_64K,
  159. .type = MT_DEVICE,
  160. },
  161. {
  162. .virtual = U300_AHB_PER_VIRT_BASE,
  163. .pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  164. .length = SZ_32K,
  165. .type = MT_DEVICE,
  166. },
  167. {
  168. .virtual = U300_FAST_PER_VIRT_BASE,
  169. .pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  170. .length = SZ_32K,
  171. .type = MT_DEVICE,
  172. },
  173. };
  174. static void __init u300_map_io(void)
  175. {
  176. iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  177. }
  178. static unsigned long pin_pullup_conf[] = {
  179. PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
  180. };
  181. static unsigned long pin_highz_conf[] = {
  182. PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
  183. };
  184. /* Pin control settings */
  185. static const struct pinctrl_map u300_pinmux_map[] = {
  186. /* anonymous maps for chip power and EMIFs */
  187. PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
  188. PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
  189. PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
  190. /* per-device maps for MMC/SD, SPI and UART */
  191. PIN_MAP_MUX_GROUP_DEFAULT("mmci", "pinctrl-u300", NULL, "mmc0"),
  192. PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
  193. PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
  194. /* This pin is used for clock return rather than GPIO */
  195. PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
  196. pin_pullup_conf),
  197. /* This pin is used for card detect */
  198. PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
  199. pin_highz_conf),
  200. };
  201. struct db_chip {
  202. u16 chipid;
  203. const char *name;
  204. };
  205. /*
  206. * This is a list of the Digital Baseband chips used in the U300 platform.
  207. */
  208. static struct db_chip db_chips[] __initdata = {
  209. {
  210. .chipid = 0xb800,
  211. .name = "DB3000",
  212. },
  213. {
  214. .chipid = 0xc000,
  215. .name = "DB3100",
  216. },
  217. {
  218. .chipid = 0xc800,
  219. .name = "DB3150",
  220. },
  221. {
  222. .chipid = 0xd800,
  223. .name = "DB3200",
  224. },
  225. {
  226. .chipid = 0xe000,
  227. .name = "DB3250",
  228. },
  229. {
  230. .chipid = 0xe800,
  231. .name = "DB3210",
  232. },
  233. {
  234. .chipid = 0xf000,
  235. .name = "DB3350 P1x",
  236. },
  237. {
  238. .chipid = 0xf100,
  239. .name = "DB3350 P2x",
  240. },
  241. {
  242. .chipid = 0x0000, /* List terminator */
  243. .name = NULL,
  244. }
  245. };
  246. static void __init u300_init_check_chip(void)
  247. {
  248. u16 val;
  249. struct db_chip *chip;
  250. const char *chipname;
  251. const char unknown[] = "UNKNOWN";
  252. /* Read out and print chip ID */
  253. val = readw(syscon_base + U300_SYSCON_CIDR);
  254. /* This is in funky bigendian order... */
  255. val = (val & 0xFFU) << 8 | (val >> 8);
  256. chip = db_chips;
  257. chipname = unknown;
  258. for ( ; chip->chipid; chip++) {
  259. if (chip->chipid == (val & 0xFF00U)) {
  260. chipname = chip->name;
  261. break;
  262. }
  263. }
  264. printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
  265. "(chip ID 0x%04x)\n", chipname, val);
  266. if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
  267. printk(KERN_ERR "Platform configured for BS335 " \
  268. " with DB3350 but %s detected, expect problems!",
  269. chipname);
  270. }
  271. }
  272. /* Forward declare this function from the watchdog */
  273. void coh901327_watchdog_reset(void);
  274. static void u300_restart(enum reboot_mode mode, const char *cmd)
  275. {
  276. switch (mode) {
  277. case REBOOT_SOFT:
  278. case REBOOT_HARD:
  279. #ifdef CONFIG_COH901327_WATCHDOG
  280. coh901327_watchdog_reset();
  281. #endif
  282. break;
  283. default:
  284. /* Do nothing */
  285. break;
  286. }
  287. /* Wait for system do die/reset. */
  288. while (1);
  289. }
  290. /* These are mostly to get the right device names for the clock lookups */
  291. static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
  292. OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
  293. "pinctrl-u300", NULL),
  294. OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
  295. "u300-gpio", NULL),
  296. OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE,
  297. "coh901327_wdog", NULL),
  298. OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE,
  299. "rtc-coh901331", NULL),
  300. OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE,
  301. "coh901318", NULL),
  302. OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
  303. "fsmc-nand", NULL),
  304. OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
  305. "uart0", NULL),
  306. OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
  307. "uart1", NULL),
  308. OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
  309. "pl022", NULL),
  310. OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
  311. "stu300.0", NULL),
  312. OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
  313. "stu300.1", NULL),
  314. OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
  315. "mmci", NULL),
  316. { /* sentinel */ },
  317. };
  318. static void __init u300_init_irq_dt(void)
  319. {
  320. struct device_node *syscon;
  321. struct clk *clk;
  322. syscon = of_find_node_by_path("/syscon@c0011000");
  323. if (!syscon) {
  324. pr_crit("could not find syscon node\n");
  325. return;
  326. }
  327. syscon_base = of_iomap(syscon, 0);
  328. if (!syscon_base) {
  329. pr_crit("could not remap syscon\n");
  330. return;
  331. }
  332. /* initialize clocking early, we want to clock the INTCON */
  333. u300_clk_init(syscon_base);
  334. /* Bootstrap EMIF and SEMI clocks */
  335. clk = clk_get_sys("pl172", NULL);
  336. BUG_ON(IS_ERR(clk));
  337. clk_prepare_enable(clk);
  338. clk = clk_get_sys("semi", NULL);
  339. BUG_ON(IS_ERR(clk));
  340. clk_prepare_enable(clk);
  341. /* Clock the interrupt controller */
  342. clk = clk_get_sys("intcon", NULL);
  343. BUG_ON(IS_ERR(clk));
  344. clk_prepare_enable(clk);
  345. irqchip_init();
  346. }
  347. static void __init u300_init_machine_dt(void)
  348. {
  349. u16 val;
  350. /* Check what platform we run and print some status information */
  351. u300_init_check_chip();
  352. /* Initialize pinmuxing */
  353. pinctrl_register_mappings(u300_pinmux_map,
  354. ARRAY_SIZE(u300_pinmux_map));
  355. of_platform_default_populate(NULL, u300_auxdata_lookup, NULL);
  356. /* Enable SEMI self refresh */
  357. val = readw(syscon_base + U300_SYSCON_SMCR) |
  358. U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
  359. writew(val, syscon_base + U300_SYSCON_SMCR);
  360. }
  361. static const char * u300_board_compat[] = {
  362. "stericsson,u300",
  363. NULL,
  364. };
  365. DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
  366. .map_io = u300_map_io,
  367. .init_irq = u300_init_irq_dt,
  368. .init_time = timer_probe,
  369. .init_machine = u300_init_machine_dt,
  370. .restart = u300_restart,
  371. .dt_compat = u300_board_compat,
  372. MACHINE_END