platsmp.c 2.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * arch/arm/mach-sti/platsmp.c
  4. *
  5. * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
  6. * http://www.st.com
  7. *
  8. * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
  9. *
  10. * Copyright (C) 2002 ARM Ltd.
  11. * All Rights Reserved
  12. */
  13. #include <linux/init.h>
  14. #include <linux/errno.h>
  15. #include <linux/delay.h>
  16. #include <linux/smp.h>
  17. #include <linux/io.h>
  18. #include <linux/of.h>
  19. #include <linux/of_address.h>
  20. #include <linux/memblock.h>
  21. #include <asm/cacheflush.h>
  22. #include <asm/smp_plat.h>
  23. #include <asm/smp_scu.h>
  24. #include "smp.h"
  25. static u32 __iomem *cpu_strt_ptr;
  26. static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
  27. {
  28. unsigned long entry_pa = __pa_symbol(secondary_startup);
  29. /*
  30. * Secondary CPU is initialised and started by a U-BOOTROM firmware.
  31. * Secondary CPU is spinning and waiting for a write at cpu_strt_ptr.
  32. * Writing secondary_startup address at cpu_strt_ptr makes it to
  33. * jump directly to secondary_startup().
  34. */
  35. __raw_writel(entry_pa, cpu_strt_ptr);
  36. /* wmb so that data is actually written before cache flush is done */
  37. smp_wmb();
  38. sync_cache_w(cpu_strt_ptr);
  39. return 0;
  40. }
  41. static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
  42. {
  43. struct device_node *np;
  44. void __iomem *scu_base;
  45. u32 release_phys;
  46. int cpu;
  47. np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
  48. if (np) {
  49. scu_base = of_iomap(np, 0);
  50. scu_enable(scu_base);
  51. of_node_put(np);
  52. }
  53. if (max_cpus <= 1)
  54. return;
  55. for_each_possible_cpu(cpu) {
  56. np = of_get_cpu_node(cpu, NULL);
  57. if (!np)
  58. continue;
  59. if (of_property_read_u32(np, "cpu-release-addr",
  60. &release_phys)) {
  61. pr_err("CPU %d: missing or invalid cpu-release-addr "
  62. "property\n", cpu);
  63. continue;
  64. }
  65. /*
  66. * cpu-release-addr is usually configured in SBC DMEM but can
  67. * also be in RAM.
  68. */
  69. if (!memblock_is_memory(release_phys))
  70. cpu_strt_ptr =
  71. ioremap(release_phys, sizeof(release_phys));
  72. else
  73. cpu_strt_ptr =
  74. (u32 __iomem *)phys_to_virt(release_phys);
  75. set_cpu_possible(cpu, true);
  76. }
  77. }
  78. const struct smp_operations sti_smp_ops __initconst = {
  79. .smp_prepare_cpus = sti_smp_prepare_cpus,
  80. .smp_boot_secondary = sti_boot_secondary,
  81. };