pm-rcar-gen2.c 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R-Car Generation 2 Power management support
  4. *
  5. * Copyright (C) 2013 - 2015 Renesas Electronics Corporation
  6. * Copyright (C) 2011 Renesas Solutions Corp.
  7. * Copyright (C) 2011 Magnus Damm
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/ioport.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <linux/smp.h>
  14. #include <asm/io.h>
  15. #include <asm/cputype.h>
  16. #include "common.h"
  17. #include "rcar-gen2.h"
  18. /* RST */
  19. #define RST 0xe6160000
  20. #define CA15BAR 0x0020 /* CA15 Boot Address Register */
  21. #define CA7BAR 0x0030 /* CA7 Boot Address Register */
  22. #define CA15RESCNT 0x0040 /* CA15 Reset Control Register */
  23. #define CA7RESCNT 0x0044 /* CA7 Reset Control Register */
  24. /* SYS Boot Address Register */
  25. #define SBAR_BAREN BIT(4) /* SBAR is valid */
  26. /* Reset Control Registers */
  27. #define CA15RESCNT_CODE 0xa5a50000
  28. #define CA15RESCNT_CPUS 0xf /* CPU0-3 */
  29. #define CA7RESCNT_CODE 0x5a5a0000
  30. #define CA7RESCNT_CPUS 0xf /* CPU0-3 */
  31. /* On-chip RAM */
  32. #define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */
  33. static inline u32 phys_to_sbar(phys_addr_t addr)
  34. {
  35. return (addr >> 8) & 0xfffffc00;
  36. }
  37. void __init rcar_gen2_pm_init(void)
  38. {
  39. void __iomem *p;
  40. u32 bar;
  41. static int once;
  42. struct device_node *np;
  43. bool has_a7 = false;
  44. bool has_a15 = false;
  45. struct resource res;
  46. int error;
  47. if (once++)
  48. return;
  49. for_each_of_cpu_node(np) {
  50. if (of_device_is_compatible(np, "arm,cortex-a15"))
  51. has_a15 = true;
  52. else if (of_device_is_compatible(np, "arm,cortex-a7"))
  53. has_a7 = true;
  54. }
  55. np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram");
  56. if (!np) {
  57. /* No smp-sram in DT, fall back to hardcoded address */
  58. res = (struct resource)DEFINE_RES_MEM(ICRAM1,
  59. shmobile_boot_size);
  60. goto map;
  61. }
  62. error = of_address_to_resource(np, 0, &res);
  63. of_node_put(np);
  64. if (error) {
  65. pr_err("Failed to get smp-sram address: %d\n", error);
  66. return;
  67. }
  68. map:
  69. /* RAM for jump stub, because BAR requires 256KB aligned address */
  70. if (res.start & (256 * 1024 - 1) ||
  71. resource_size(&res) < shmobile_boot_size) {
  72. pr_err("Invalid smp-sram region\n");
  73. return;
  74. }
  75. p = ioremap(res.start, resource_size(&res));
  76. if (!p)
  77. return;
  78. /*
  79. * install the reset vector, use the largest version if we have enough
  80. * memory available
  81. */
  82. if (resource_size(&res) >= shmobile_boot_size_gen2) {
  83. shmobile_boot_cpu_gen2 = read_cpuid_mpidr();
  84. memcpy_toio(p, shmobile_boot_vector_gen2,
  85. shmobile_boot_size_gen2);
  86. } else {
  87. memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
  88. }
  89. iounmap(p);
  90. /* setup reset vectors */
  91. p = ioremap(RST, 0x63);
  92. bar = phys_to_sbar(res.start);
  93. if (has_a15) {
  94. writel_relaxed(bar, p + CA15BAR);
  95. writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
  96. /* de-assert reset for CA15 CPUs */
  97. writel_relaxed((readl_relaxed(p + CA15RESCNT) &
  98. ~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
  99. p + CA15RESCNT);
  100. }
  101. if (has_a7) {
  102. writel_relaxed(bar, p + CA7BAR);
  103. writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
  104. /* de-assert reset for CA7 CPUs */
  105. writel_relaxed((readl_relaxed(p + CA7RESCNT) &
  106. ~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
  107. p + CA7RESCNT);
  108. }
  109. iounmap(p);
  110. shmobile_smp_apmu_suspend_init();
  111. }