platsmp-apmu.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SMP support for SoCs with APMU
  4. *
  5. * Copyright (C) 2014 Renesas Electronics Corporation
  6. * Copyright (C) 2013 Magnus Damm
  7. */
  8. #include <linux/cpu_pm.h>
  9. #include <linux/delay.h>
  10. #include <linux/init.h>
  11. #include <linux/io.h>
  12. #include <linux/ioport.h>
  13. #include <linux/of_address.h>
  14. #include <linux/smp.h>
  15. #include <linux/suspend.h>
  16. #include <linux/threads.h>
  17. #include <asm/cacheflush.h>
  18. #include <asm/cp15.h>
  19. #include <asm/proc-fns.h>
  20. #include <asm/smp_plat.h>
  21. #include <asm/suspend.h>
  22. #include "common.h"
  23. #include "rcar-gen2.h"
  24. static struct {
  25. void __iomem *iomem;
  26. int bit;
  27. } apmu_cpus[NR_CPUS];
  28. #define WUPCR_OFFS 0x10 /* Wake Up Control Register */
  29. #define PSTR_OFFS 0x40 /* Power Status Register */
  30. #define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))
  31. /* CPUn Power Status Control Register */
  32. #define DBGRCR_OFFS 0x180 /* Debug Resource Reset Control Reg. */
  33. /* Power Status Register */
  34. #define CPUNST(r, n) (((r) >> (n * 4)) & 3) /* CPUn Status Bit */
  35. #define CPUST_RUN 0 /* Run Mode */
  36. #define CPUST_STANDBY 3 /* CoreStandby Mode */
  37. /* Debug Resource Reset Control Register */
  38. #define DBGCPUREN BIT(24) /* CPU Other Reset Request Enable */
  39. #define DBGCPUNREN(n) BIT((n) + 20) /* CPUn Reset Request Enable */
  40. #define DBGCPUPREN BIT(19) /* CPU Peripheral Reset Req. Enable */
  41. static int __maybe_unused apmu_power_on(void __iomem *p, int bit)
  42. {
  43. /* request power on */
  44. writel_relaxed(BIT(bit), p + WUPCR_OFFS);
  45. /* wait for APMU to finish */
  46. while (readl_relaxed(p + WUPCR_OFFS) != 0)
  47. ;
  48. return 0;
  49. }
  50. static int __maybe_unused apmu_power_off(void __iomem *p, int bit)
  51. {
  52. /* request Core Standby for next WFI */
  53. writel_relaxed(3, p + CPUNCR_OFFS(bit));
  54. return 0;
  55. }
  56. static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit)
  57. {
  58. int k;
  59. for (k = 0; k < 1000; k++) {
  60. if (CPUNST(readl_relaxed(p + PSTR_OFFS), bit) == CPUST_STANDBY)
  61. return 1;
  62. mdelay(1);
  63. }
  64. return 0;
  65. }
  66. static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu))
  67. {
  68. void __iomem *p = apmu_cpus[cpu].iomem;
  69. return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL;
  70. }
  71. #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_SUSPEND)
  72. /* nicked from arch/arm/mach-exynos/hotplug.c */
  73. static inline void cpu_enter_lowpower_a15(void)
  74. {
  75. unsigned int v;
  76. asm volatile(
  77. " mrc p15, 0, %0, c1, c0, 0\n"
  78. " bic %0, %0, %1\n"
  79. " mcr p15, 0, %0, c1, c0, 0\n"
  80. : "=&r" (v)
  81. : "Ir" (CR_C)
  82. : "cc");
  83. flush_cache_louis();
  84. asm volatile(
  85. /*
  86. * Turn off coherency
  87. */
  88. " mrc p15, 0, %0, c1, c0, 1\n"
  89. " bic %0, %0, %1\n"
  90. " mcr p15, 0, %0, c1, c0, 1\n"
  91. : "=&r" (v)
  92. : "Ir" (0x40)
  93. : "cc");
  94. isb();
  95. dsb();
  96. }
  97. static void shmobile_smp_apmu_cpu_shutdown(unsigned int cpu)
  98. {
  99. /* Select next sleep mode using the APMU */
  100. apmu_wrap(cpu, apmu_power_off);
  101. /* Do ARM specific CPU shutdown */
  102. cpu_enter_lowpower_a15();
  103. }
  104. #endif
  105. #if defined(CONFIG_HOTPLUG_CPU)
  106. static void shmobile_smp_apmu_cpu_die(unsigned int cpu)
  107. {
  108. /* For this particular CPU deregister boot vector */
  109. shmobile_smp_hook(cpu, 0, 0);
  110. /* Shutdown CPU core */
  111. shmobile_smp_apmu_cpu_shutdown(cpu);
  112. /* jump to shared mach-shmobile sleep / reset code */
  113. shmobile_smp_sleep();
  114. }
  115. static int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
  116. {
  117. return apmu_wrap(cpu, apmu_power_off_poll);
  118. }
  119. #endif
  120. #if defined(CONFIG_SUSPEND)
  121. static int shmobile_smp_apmu_do_suspend(unsigned long cpu)
  122. {
  123. shmobile_smp_hook(cpu, __pa_symbol(cpu_resume), 0);
  124. shmobile_smp_apmu_cpu_shutdown(cpu);
  125. cpu_do_idle(); /* WFI selects Core Standby */
  126. return 1;
  127. }
  128. static inline void cpu_leave_lowpower(void)
  129. {
  130. unsigned int v;
  131. asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
  132. " orr %0, %0, %1\n"
  133. " mcr p15, 0, %0, c1, c0, 0\n"
  134. " mrc p15, 0, %0, c1, c0, 1\n"
  135. " orr %0, %0, %2\n"
  136. " mcr p15, 0, %0, c1, c0, 1\n"
  137. : "=&r" (v)
  138. : "Ir" (CR_C), "Ir" (0x40)
  139. : "cc");
  140. }
  141. static int shmobile_smp_apmu_enter_suspend(suspend_state_t state)
  142. {
  143. cpu_suspend(smp_processor_id(), shmobile_smp_apmu_do_suspend);
  144. cpu_leave_lowpower();
  145. return 0;
  146. }
  147. void __init shmobile_smp_apmu_suspend_init(void)
  148. {
  149. shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend;
  150. }
  151. #endif
  152. #ifdef CONFIG_SMP
  153. static void apmu_init_cpu(struct resource *res, int cpu, int bit)
  154. {
  155. u32 x;
  156. if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem)
  157. return;
  158. apmu_cpus[cpu].iomem = ioremap(res->start, resource_size(res));
  159. apmu_cpus[cpu].bit = bit;
  160. pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);
  161. /* Setup for debug mode */
  162. x = readl(apmu_cpus[cpu].iomem + DBGRCR_OFFS);
  163. x |= DBGCPUREN | DBGCPUNREN(bit) | DBGCPUPREN;
  164. writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS);
  165. }
  166. static const struct of_device_id apmu_ids[] = {
  167. { .compatible = "renesas,apmu" },
  168. { /*sentinel*/ }
  169. };
  170. static void apmu_parse_dt(void (*fn)(struct resource *res, int cpu, int bit))
  171. {
  172. struct device_node *np_apmu, *np_cpu;
  173. struct resource res;
  174. int bit, index;
  175. u32 id;
  176. for_each_matching_node(np_apmu, apmu_ids) {
  177. /* only enable the cluster that includes the boot CPU */
  178. bool is_allowed = false;
  179. for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
  180. np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
  181. if (np_cpu) {
  182. if (!of_property_read_u32(np_cpu, "reg", &id)) {
  183. if (id == cpu_logical_map(0)) {
  184. is_allowed = true;
  185. of_node_put(np_cpu);
  186. break;
  187. }
  188. }
  189. of_node_put(np_cpu);
  190. }
  191. }
  192. if (!is_allowed)
  193. continue;
  194. for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
  195. np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
  196. if (np_cpu) {
  197. if (!of_property_read_u32(np_cpu, "reg", &id)) {
  198. index = get_logical_index(id);
  199. if ((index >= 0) &&
  200. !of_address_to_resource(np_apmu,
  201. 0, &res))
  202. fn(&res, index, bit);
  203. }
  204. of_node_put(np_cpu);
  205. }
  206. }
  207. }
  208. }
  209. static void __init shmobile_smp_apmu_setup_boot(void)
  210. {
  211. /* install boot code shared by all CPUs */
  212. shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
  213. shmobile_boot_fn_gen2 = shmobile_boot_fn;
  214. }
  215. static int shmobile_smp_apmu_boot_secondary(unsigned int cpu,
  216. struct task_struct *idle)
  217. {
  218. /* For this particular CPU register boot vector */
  219. shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_apmu), 0);
  220. return apmu_wrap(cpu, apmu_power_on);
  221. }
  222. static void __init shmobile_smp_apmu_prepare_cpus_dt(unsigned int max_cpus)
  223. {
  224. shmobile_smp_apmu_setup_boot();
  225. apmu_parse_dt(apmu_init_cpu);
  226. rcar_gen2_pm_init();
  227. }
  228. static struct smp_operations apmu_smp_ops __initdata = {
  229. .smp_prepare_cpus = shmobile_smp_apmu_prepare_cpus_dt,
  230. .smp_boot_secondary = shmobile_smp_apmu_boot_secondary,
  231. #ifdef CONFIG_HOTPLUG_CPU
  232. .cpu_can_disable = shmobile_smp_cpu_can_disable,
  233. .cpu_die = shmobile_smp_apmu_cpu_die,
  234. .cpu_kill = shmobile_smp_apmu_cpu_kill,
  235. #endif
  236. };
  237. CPU_METHOD_OF_DECLARE(shmobile_smp_apmu, "renesas,apmu", &apmu_smp_ops);
  238. #endif /* CONFIG_SMP */