pmsu_ll.S 2.0 KB

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  1. /*
  2. * Copyright (C) 2014 Marvell
  3. *
  4. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  5. * Gregory Clement <gregory.clement@free-electrons.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/linkage.h>
  12. #include <asm/assembler.h>
  13. ENTRY(armada_38x_scu_power_up)
  14. mrc p15, 4, r1, c15, c0 @ get SCU base address
  15. orr r1, r1, #0x8 @ SCU CPU Power Status Register
  16. mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID
  17. and r0, r0, #15
  18. add r1, r1, r0
  19. mov r0, #0x0
  20. strb r0, [r1] @ switch SCU power state to Normal mode
  21. ret lr
  22. ENDPROC(armada_38x_scu_power_up)
  23. /*
  24. * This is the entry point through which CPUs exiting cpuidle deep
  25. * idle state are going.
  26. */
  27. ENTRY(armada_370_xp_cpu_resume)
  28. ARM_BE8(setend be ) @ go BE8 if entered LE
  29. /*
  30. * Disable the MMU that might have been enabled in BootROM if
  31. * this code is used in the resume path of a suspend/resume
  32. * cycle.
  33. */
  34. mrc p15, 0, r1, c1, c0, 0
  35. bic r1, #1
  36. mcr p15, 0, r1, c1, c0, 0
  37. bl ll_add_cpu_to_smp_group
  38. bl ll_enable_coherency
  39. b cpu_resume
  40. ENDPROC(armada_370_xp_cpu_resume)
  41. ENTRY(armada_38x_cpu_resume)
  42. /* do we need it for Armada 38x*/
  43. ARM_BE8(setend be ) @ go BE8 if entered LE
  44. bl v7_invalidate_l1
  45. bl armada_38x_scu_power_up
  46. b cpu_resume
  47. ENDPROC(armada_38x_cpu_resume)
  48. .global mvebu_boot_wa_start
  49. .global mvebu_boot_wa_end
  50. /* The following code will be executed from SRAM */
  51. ENTRY(mvebu_boot_wa_start)
  52. ARM_BE8(setend be)
  53. adr r0, 1f
  54. ldr r0, [r0] @ load the address of the
  55. @ resume register
  56. ldr r0, [r0] @ load the value in the
  57. @ resume register
  58. ARM_BE8(rev r0, r0) @ the value is stored LE
  59. mov pc, r0 @ jump to this value
  60. /*
  61. * the last word of this piece of code will be filled by the physical
  62. * address of the boot address register just after being copied in SRAM
  63. */
  64. 1:
  65. .long .
  66. mvebu_boot_wa_end:
  67. ENDPROC(mvebu_boot_wa_end)