mstarv7.c 2.3 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree support for MStar/Sigmastar Armv7 SoCs
  4. *
  5. * Copyright (c) 2020 thingy.jp
  6. * Author: Daniel Palmer <daniel@thingy.jp>
  7. */
  8. #include <linux/init.h>
  9. #include <asm/mach/arch.h>
  10. #include <asm/mach/map.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <linux/io.h>
  14. /*
  15. * In the u-boot code the area these registers are in is
  16. * called "L3 bridge" and there are register descriptions
  17. * for something in the same area called "AXI".
  18. *
  19. * It's not exactly known what this is but the vendor code
  20. * for both u-boot and linux share calls to "flush the miu pipe".
  21. * This seems to be to force pending CPU writes to memory so that
  22. * the state is right before DMA capable devices try to read
  23. * descriptors and data the CPU has prepared. Without doing this
  24. * ethernet doesn't work reliably for example.
  25. */
  26. #define MSTARV7_L3BRIDGE_FLUSH 0x14
  27. #define MSTARV7_L3BRIDGE_STATUS 0x40
  28. #define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0)
  29. #define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12)
  30. static void __iomem *l3bridge;
  31. static const char * const mstarv7_board_dt_compat[] __initconst = {
  32. "mstar,infinity",
  33. "mstar,infinity3",
  34. "mstar,mercury5",
  35. NULL,
  36. };
  37. /*
  38. * This may need locking to deal with situations where an interrupt
  39. * happens while we are in here and mb() gets called by the interrupt handler.
  40. *
  41. * The vendor code did have a spin lock but it doesn't seem to be needed and
  42. * removing it hasn't caused any side effects so far.
  43. *
  44. * [writel|readl]_relaxed have to be used here because otherwise
  45. * we'd end up right back in here.
  46. */
  47. static void mstarv7_mb(void)
  48. {
  49. /* toggle the flush miu pipe fire bit */
  50. writel_relaxed(0, l3bridge + MSTARV7_L3BRIDGE_FLUSH);
  51. writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, l3bridge
  52. + MSTARV7_L3BRIDGE_FLUSH);
  53. while (!(readl_relaxed(l3bridge + MSTARV7_L3BRIDGE_STATUS)
  54. & MSTARV7_L3BRIDGE_STATUS_DONE)) {
  55. /* wait for flush to complete */
  56. }
  57. }
  58. static void __init mstarv7_init(void)
  59. {
  60. struct device_node *np;
  61. np = of_find_compatible_node(NULL, NULL, "mstar,l3bridge");
  62. l3bridge = of_iomap(np, 0);
  63. if (l3bridge)
  64. soc_mb = mstarv7_mb;
  65. else
  66. pr_warn("Failed to install memory barrier, DMA will be broken!\n");
  67. }
  68. DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)")
  69. .dt_compat = mstarv7_board_dt_compat,
  70. .init_machine = mstarv7_init,
  71. MACHINE_END