vulcan-pci.c 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * arch/arch/mach-ixp4xx/vulcan-pci.c
  4. *
  5. * Vulcan board-level PCI initialization
  6. *
  7. * Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
  8. *
  9. * based on ixdp425-pci.c:
  10. * Copyright (C) 2002 Intel Corporation.
  11. * Copyright (C) 2003-2004 MontaVista Software, Inc.
  12. */
  13. #include <linux/pci.h>
  14. #include <linux/init.h>
  15. #include <linux/irq.h>
  16. #include <asm/mach/pci.h>
  17. #include <asm/mach-types.h>
  18. #include "irqs.h"
  19. /* PCI controller GPIO to IRQ pin mappings */
  20. #define INTA 2
  21. #define INTB 3
  22. void __init vulcan_pci_preinit(void)
  23. {
  24. #ifndef CONFIG_IXP4XX_INDIRECT_PCI
  25. /*
  26. * Cardbus bridge wants way more than the SoC can actually offer,
  27. * and leaves the whole PCI bus in a mess. Artificially limit it
  28. * to 8MB per region. Of course indirect mode doesn't have this
  29. * limitation...
  30. */
  31. pci_cardbus_mem_size = SZ_8M;
  32. pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
  33. (int)(pci_cardbus_mem_size >> 20));
  34. #endif
  35. irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
  36. irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
  37. ixp4xx_pci_preinit();
  38. }
  39. static int __init vulcan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  40. {
  41. if (slot == 1)
  42. return IXP4XX_GPIO_IRQ(INTA);
  43. if (slot == 2)
  44. return IXP4XX_GPIO_IRQ(INTB);
  45. return -1;
  46. }
  47. struct hw_pci vulcan_pci __initdata = {
  48. .nr_controllers = 1,
  49. .ops = &ixp4xx_ops,
  50. .preinit = vulcan_pci_preinit,
  51. .setup = ixp4xx_setup,
  52. .map_irq = vulcan_map_irq,
  53. };
  54. int __init vulcan_pci_init(void)
  55. {
  56. if (machine_is_arcom_vulcan())
  57. pci_common_init(&vulcan_pci);
  58. return 0;
  59. }
  60. subsys_initcall(vulcan_pci_init);