ixdp425-setup.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * arch/arm/mach-ixp4xx/ixdp425-setup.c
  4. *
  5. * IXDP425/IXCDP1100 board-setup
  6. *
  7. * Copyright (C) 2003-2005 MontaVista Software, Inc.
  8. *
  9. * Author: Deepak Saxena <dsaxena@plexity.net>
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/device.h>
  14. #include <linux/serial.h>
  15. #include <linux/tty.h>
  16. #include <linux/serial_8250.h>
  17. #include <linux/gpio/machine.h>
  18. #include <linux/io.h>
  19. #include <linux/mtd/mtd.h>
  20. #include <linux/mtd/rawnand.h>
  21. #include <linux/mtd/partitions.h>
  22. #include <linux/mtd/platnand.h>
  23. #include <linux/delay.h>
  24. #include <linux/gpio.h>
  25. #include <asm/types.h>
  26. #include <asm/setup.h>
  27. #include <asm/memory.h>
  28. #include <mach/hardware.h>
  29. #include <asm/mach-types.h>
  30. #include <asm/irq.h>
  31. #include <asm/mach/arch.h>
  32. #include <asm/mach/flash.h>
  33. #include "irqs.h"
  34. #define IXDP425_SDA_PIN 7
  35. #define IXDP425_SCL_PIN 6
  36. /* NAND Flash pins */
  37. #define IXDP425_NAND_NCE_PIN 12
  38. #define IXDP425_NAND_CMD_BYTE 0x01
  39. #define IXDP425_NAND_ADDR_BYTE 0x02
  40. static struct flash_platform_data ixdp425_flash_data = {
  41. .map_name = "cfi_probe",
  42. .width = 2,
  43. };
  44. static struct resource ixdp425_flash_resource = {
  45. .flags = IORESOURCE_MEM,
  46. };
  47. static struct platform_device ixdp425_flash = {
  48. .name = "IXP4XX-Flash",
  49. .id = 0,
  50. .dev = {
  51. .platform_data = &ixdp425_flash_data,
  52. },
  53. .num_resources = 1,
  54. .resource = &ixdp425_flash_resource,
  55. };
  56. #if defined(CONFIG_MTD_NAND_PLATFORM) || \
  57. defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
  58. static struct mtd_partition ixdp425_partitions[] = {
  59. {
  60. .name = "ixp400 NAND FS 0",
  61. .offset = 0,
  62. .size = SZ_8M
  63. }, {
  64. .name = "ixp400 NAND FS 1",
  65. .offset = MTDPART_OFS_APPEND,
  66. .size = MTDPART_SIZ_FULL
  67. },
  68. };
  69. static void
  70. ixdp425_flash_nand_cmd_ctrl(struct nand_chip *this, int cmd, unsigned int ctrl)
  71. {
  72. int offset = (int)nand_get_controller_data(this);
  73. if (ctrl & NAND_CTRL_CHANGE) {
  74. if (ctrl & NAND_NCE) {
  75. gpio_set_value(IXDP425_NAND_NCE_PIN, 0);
  76. udelay(5);
  77. } else
  78. gpio_set_value(IXDP425_NAND_NCE_PIN, 1);
  79. offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0;
  80. offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0;
  81. nand_set_controller_data(this, (void *)offset);
  82. }
  83. if (cmd != NAND_CMD_NONE)
  84. writeb(cmd, this->legacy.IO_ADDR_W + offset);
  85. }
  86. static struct platform_nand_data ixdp425_flash_nand_data = {
  87. .chip = {
  88. .nr_chips = 1,
  89. .chip_delay = 30,
  90. .partitions = ixdp425_partitions,
  91. .nr_partitions = ARRAY_SIZE(ixdp425_partitions),
  92. },
  93. .ctrl = {
  94. .cmd_ctrl = ixdp425_flash_nand_cmd_ctrl
  95. }
  96. };
  97. static struct resource ixdp425_flash_nand_resource = {
  98. .flags = IORESOURCE_MEM,
  99. };
  100. static struct platform_device ixdp425_flash_nand = {
  101. .name = "gen_nand",
  102. .id = -1,
  103. .dev = {
  104. .platform_data = &ixdp425_flash_nand_data,
  105. },
  106. .num_resources = 1,
  107. .resource = &ixdp425_flash_nand_resource,
  108. };
  109. #endif /* CONFIG_MTD_NAND_PLATFORM */
  110. static struct gpiod_lookup_table ixdp425_i2c_gpiod_table = {
  111. .dev_id = "i2c-gpio.0",
  112. .table = {
  113. GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SDA_PIN,
  114. NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
  115. GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SCL_PIN,
  116. NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
  117. },
  118. };
  119. static struct platform_device ixdp425_i2c_gpio = {
  120. .name = "i2c-gpio",
  121. .id = 0,
  122. .dev = {
  123. .platform_data = NULL,
  124. },
  125. };
  126. static struct resource ixdp425_uart_resources[] = {
  127. {
  128. .start = IXP4XX_UART1_BASE_PHYS,
  129. .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
  130. .flags = IORESOURCE_MEM
  131. },
  132. {
  133. .start = IXP4XX_UART2_BASE_PHYS,
  134. .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
  135. .flags = IORESOURCE_MEM
  136. }
  137. };
  138. static struct plat_serial8250_port ixdp425_uart_data[] = {
  139. {
  140. .mapbase = IXP4XX_UART1_BASE_PHYS,
  141. .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
  142. .irq = IRQ_IXP4XX_UART1,
  143. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  144. .iotype = UPIO_MEM,
  145. .regshift = 2,
  146. .uartclk = IXP4XX_UART_XTAL,
  147. },
  148. {
  149. .mapbase = IXP4XX_UART2_BASE_PHYS,
  150. .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
  151. .irq = IRQ_IXP4XX_UART2,
  152. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  153. .iotype = UPIO_MEM,
  154. .regshift = 2,
  155. .uartclk = IXP4XX_UART_XTAL,
  156. },
  157. { },
  158. };
  159. static struct platform_device ixdp425_uart = {
  160. .name = "serial8250",
  161. .id = PLAT8250_DEV_PLATFORM,
  162. .dev.platform_data = ixdp425_uart_data,
  163. .num_resources = 2,
  164. .resource = ixdp425_uart_resources
  165. };
  166. /* Built-in 10/100 Ethernet MAC interfaces */
  167. static struct resource ixp425_npeb_resources[] = {
  168. {
  169. .start = IXP4XX_EthB_BASE_PHYS,
  170. .end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
  171. .flags = IORESOURCE_MEM,
  172. },
  173. };
  174. static struct resource ixp425_npec_resources[] = {
  175. {
  176. .start = IXP4XX_EthC_BASE_PHYS,
  177. .end = IXP4XX_EthC_BASE_PHYS + 0x0fff,
  178. .flags = IORESOURCE_MEM,
  179. },
  180. };
  181. static struct eth_plat_info ixdp425_plat_eth[] = {
  182. {
  183. .phy = 0,
  184. .rxq = 3,
  185. .txreadyq = 20,
  186. }, {
  187. .phy = 1,
  188. .rxq = 4,
  189. .txreadyq = 21,
  190. }
  191. };
  192. static struct platform_device ixdp425_eth[] = {
  193. {
  194. .name = "ixp4xx_eth",
  195. .id = IXP4XX_ETH_NPEB,
  196. .dev.platform_data = ixdp425_plat_eth,
  197. .num_resources = ARRAY_SIZE(ixp425_npeb_resources),
  198. .resource = ixp425_npeb_resources,
  199. }, {
  200. .name = "ixp4xx_eth",
  201. .id = IXP4XX_ETH_NPEC,
  202. .dev.platform_data = ixdp425_plat_eth + 1,
  203. .num_resources = ARRAY_SIZE(ixp425_npec_resources),
  204. .resource = ixp425_npec_resources,
  205. }
  206. };
  207. static struct platform_device *ixdp425_devices[] __initdata = {
  208. &ixdp425_i2c_gpio,
  209. &ixdp425_flash,
  210. #if defined(CONFIG_MTD_NAND_PLATFORM) || \
  211. defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
  212. &ixdp425_flash_nand,
  213. #endif
  214. &ixdp425_uart,
  215. &ixdp425_eth[0],
  216. &ixdp425_eth[1],
  217. };
  218. static void __init ixdp425_init(void)
  219. {
  220. ixp4xx_sys_init();
  221. ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
  222. ixdp425_flash_resource.end =
  223. IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
  224. #if defined(CONFIG_MTD_NAND_PLATFORM) || \
  225. defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
  226. ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),
  227. ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;
  228. gpio_request(IXDP425_NAND_NCE_PIN, "NAND NCE pin");
  229. gpio_direction_output(IXDP425_NAND_NCE_PIN, 0);
  230. /* Configure expansion bus for NAND Flash */
  231. *IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
  232. IXP4XX_EXP_BUS_STROBE_T(1) | /* extend by 1 clock */
  233. IXP4XX_EXP_BUS_CYCLES(0) | /* Intel cycles */
  234. IXP4XX_EXP_BUS_SIZE(0) | /* 512bytes addr space*/
  235. IXP4XX_EXP_BUS_WR_EN |
  236. IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */
  237. #endif
  238. if (cpu_is_ixp43x()) {
  239. ixdp425_uart.num_resources = 1;
  240. ixdp425_uart_data[1].flags = 0;
  241. }
  242. gpiod_add_lookup_table(&ixdp425_i2c_gpiod_table);
  243. platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
  244. }
  245. #ifdef CONFIG_ARCH_IXDP425
  246. MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
  247. /* Maintainer: MontaVista Software, Inc. */
  248. .map_io = ixp4xx_map_io,
  249. .init_early = ixp4xx_init_early,
  250. .init_irq = ixp4xx_init_irq,
  251. .init_time = ixp4xx_timer_init,
  252. .atag_offset = 0x100,
  253. .init_machine = ixdp425_init,
  254. #if defined(CONFIG_PCI)
  255. .dma_zone_size = SZ_64M,
  256. #endif
  257. .restart = ixp4xx_restart,
  258. MACHINE_END
  259. #endif
  260. #ifdef CONFIG_MACH_IXDP465
  261. MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
  262. /* Maintainer: MontaVista Software, Inc. */
  263. .map_io = ixp4xx_map_io,
  264. .init_early = ixp4xx_init_early,
  265. .init_irq = ixp4xx_init_irq,
  266. .init_time = ixp4xx_timer_init,
  267. .atag_offset = 0x100,
  268. .init_machine = ixdp425_init,
  269. #if defined(CONFIG_PCI)
  270. .dma_zone_size = SZ_64M,
  271. #endif
  272. MACHINE_END
  273. #endif
  274. #ifdef CONFIG_ARCH_PRPMC1100
  275. MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
  276. /* Maintainer: MontaVista Software, Inc. */
  277. .map_io = ixp4xx_map_io,
  278. .init_early = ixp4xx_init_early,
  279. .init_irq = ixp4xx_init_irq,
  280. .init_time = ixp4xx_timer_init,
  281. .atag_offset = 0x100,
  282. .init_machine = ixdp425_init,
  283. #if defined(CONFIG_PCI)
  284. .dma_zone_size = SZ_64M,
  285. #endif
  286. MACHINE_END
  287. #endif
  288. #ifdef CONFIG_MACH_KIXRP435
  289. MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
  290. /* Maintainer: MontaVista Software, Inc. */
  291. .map_io = ixp4xx_map_io,
  292. .init_early = ixp4xx_init_early,
  293. .init_irq = ixp4xx_init_irq,
  294. .init_time = ixp4xx_timer_init,
  295. .atag_offset = 0x100,
  296. .init_machine = ixdp425_init,
  297. #if defined(CONFIG_PCI)
  298. .dma_zone_size = SZ_64M,
  299. #endif
  300. MACHINE_END
  301. #endif