common.c 8.6 KB

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  1. /*
  2. * arch/arm/mach-ixp4xx/common.c
  3. *
  4. * Generic code shared across all IXP4XX platforms
  5. *
  6. * Maintainer: Deepak Saxena <dsaxena@plexity.net>
  7. *
  8. * Copyright 2002 (c) Intel Corporation
  9. * Copyright 2003-2004 (c) MontaVista, Software, Inc.
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/mm.h>
  17. #include <linux/init.h>
  18. #include <linux/serial.h>
  19. #include <linux/tty.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/serial_core.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/bitops.h>
  24. #include <linux/io.h>
  25. #include <linux/export.h>
  26. #include <linux/cpu.h>
  27. #include <linux/pci.h>
  28. #include <linux/sched_clock.h>
  29. #include <linux/irqchip/irq-ixp4xx.h>
  30. #include <linux/platform_data/timer-ixp4xx.h>
  31. #include <linux/dma-map-ops.h>
  32. #include <mach/udc.h>
  33. #include <mach/hardware.h>
  34. #include <mach/io.h>
  35. #include <linux/uaccess.h>
  36. #include <asm/page.h>
  37. #include <asm/exception.h>
  38. #include <asm/irq.h>
  39. #include <asm/system_misc.h>
  40. #include <asm/mach/map.h>
  41. #include <asm/mach/irq.h>
  42. #include <asm/mach/time.h>
  43. #include "irqs.h"
  44. #define IXP4XX_TIMER_FREQ 66666000
  45. /*************************************************************************
  46. * IXP4xx chipset I/O mapping
  47. *************************************************************************/
  48. static struct map_desc ixp4xx_io_desc[] __initdata = {
  49. { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
  50. .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
  51. .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
  52. .length = IXP4XX_PERIPHERAL_REGION_SIZE,
  53. .type = MT_DEVICE
  54. }, { /* Expansion Bus Config Registers */
  55. .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
  56. .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
  57. .length = IXP4XX_EXP_CFG_REGION_SIZE,
  58. .type = MT_DEVICE
  59. }, { /* PCI Registers */
  60. .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
  61. .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
  62. .length = IXP4XX_PCI_CFG_REGION_SIZE,
  63. .type = MT_DEVICE
  64. },
  65. };
  66. void __init ixp4xx_map_io(void)
  67. {
  68. iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
  69. }
  70. void __init ixp4xx_init_irq(void)
  71. {
  72. /*
  73. * ixp4xx does not implement the XScale PWRMODE register
  74. * so it must not call cpu_do_idle().
  75. */
  76. cpu_idle_poll_ctrl(true);
  77. ixp4xx_irq_init(IXP4XX_INTC_BASE_PHYS,
  78. (cpu_is_ixp46x() || cpu_is_ixp43x()));
  79. }
  80. void __init ixp4xx_timer_init(void)
  81. {
  82. return ixp4xx_timer_setup(IXP4XX_TIMER_BASE_PHYS,
  83. IRQ_IXP4XX_TIMER1,
  84. IXP4XX_TIMER_FREQ);
  85. }
  86. static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
  87. void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
  88. {
  89. memcpy(&ixp4xx_udc_info, info, sizeof *info);
  90. }
  91. static struct resource ixp4xx_udc_resources[] = {
  92. [0] = {
  93. .start = 0xc800b000,
  94. .end = 0xc800bfff,
  95. .flags = IORESOURCE_MEM,
  96. },
  97. [1] = {
  98. .start = IRQ_IXP4XX_USB,
  99. .end = IRQ_IXP4XX_USB,
  100. .flags = IORESOURCE_IRQ,
  101. },
  102. };
  103. static struct resource ixp4xx_gpio_resource[] = {
  104. {
  105. .start = IXP4XX_GPIO_BASE_PHYS,
  106. .end = IXP4XX_GPIO_BASE_PHYS + 0xfff,
  107. .flags = IORESOURCE_MEM,
  108. },
  109. };
  110. static struct platform_device ixp4xx_gpio_device = {
  111. .name = "ixp4xx-gpio",
  112. .id = -1,
  113. .dev = {
  114. .coherent_dma_mask = DMA_BIT_MASK(32),
  115. },
  116. .resource = ixp4xx_gpio_resource,
  117. .num_resources = ARRAY_SIZE(ixp4xx_gpio_resource),
  118. };
  119. /*
  120. * USB device controller. The IXP4xx uses the same controller as PXA25X,
  121. * so we just use the same device.
  122. */
  123. static struct platform_device ixp4xx_udc_device = {
  124. .name = "pxa25x-udc",
  125. .id = -1,
  126. .num_resources = 2,
  127. .resource = ixp4xx_udc_resources,
  128. .dev = {
  129. .platform_data = &ixp4xx_udc_info,
  130. },
  131. };
  132. static struct resource ixp4xx_npe_resources[] = {
  133. {
  134. .start = IXP4XX_NPEA_BASE_PHYS,
  135. .end = IXP4XX_NPEA_BASE_PHYS + 0xfff,
  136. .flags = IORESOURCE_MEM,
  137. },
  138. {
  139. .start = IXP4XX_NPEB_BASE_PHYS,
  140. .end = IXP4XX_NPEB_BASE_PHYS + 0xfff,
  141. .flags = IORESOURCE_MEM,
  142. },
  143. {
  144. .start = IXP4XX_NPEC_BASE_PHYS,
  145. .end = IXP4XX_NPEC_BASE_PHYS + 0xfff,
  146. .flags = IORESOURCE_MEM,
  147. },
  148. };
  149. static struct platform_device ixp4xx_npe_device = {
  150. .name = "ixp4xx-npe",
  151. .id = -1,
  152. .num_resources = ARRAY_SIZE(ixp4xx_npe_resources),
  153. .resource = ixp4xx_npe_resources,
  154. };
  155. static struct resource ixp4xx_qmgr_resources[] = {
  156. {
  157. .start = IXP4XX_QMGR_BASE_PHYS,
  158. .end = IXP4XX_QMGR_BASE_PHYS + 0x3fff,
  159. .flags = IORESOURCE_MEM,
  160. },
  161. {
  162. .start = IRQ_IXP4XX_QM1,
  163. .end = IRQ_IXP4XX_QM1,
  164. .flags = IORESOURCE_IRQ,
  165. },
  166. {
  167. .start = IRQ_IXP4XX_QM2,
  168. .end = IRQ_IXP4XX_QM2,
  169. .flags = IORESOURCE_IRQ,
  170. },
  171. };
  172. static struct platform_device ixp4xx_qmgr_device = {
  173. .name = "ixp4xx-qmgr",
  174. .id = -1,
  175. .num_resources = ARRAY_SIZE(ixp4xx_qmgr_resources),
  176. .resource = ixp4xx_qmgr_resources,
  177. };
  178. static struct platform_device *ixp4xx_devices[] __initdata = {
  179. &ixp4xx_npe_device,
  180. &ixp4xx_qmgr_device,
  181. &ixp4xx_gpio_device,
  182. &ixp4xx_udc_device,
  183. };
  184. static struct resource ixp46x_i2c_resources[] = {
  185. [0] = {
  186. .start = 0xc8011000,
  187. .end = 0xc801101c,
  188. .flags = IORESOURCE_MEM,
  189. },
  190. [1] = {
  191. .start = IRQ_IXP4XX_I2C,
  192. .end = IRQ_IXP4XX_I2C,
  193. .flags = IORESOURCE_IRQ
  194. }
  195. };
  196. /*
  197. * I2C controller. The IXP46x uses the same block as the IOP3xx, so
  198. * we just use the same device name.
  199. */
  200. static struct platform_device ixp46x_i2c_controller = {
  201. .name = "IOP3xx-I2C",
  202. .id = 0,
  203. .num_resources = 2,
  204. .resource = ixp46x_i2c_resources
  205. };
  206. static struct platform_device *ixp46x_devices[] __initdata = {
  207. &ixp46x_i2c_controller
  208. };
  209. unsigned long ixp4xx_exp_bus_size;
  210. EXPORT_SYMBOL(ixp4xx_exp_bus_size);
  211. void __init ixp4xx_sys_init(void)
  212. {
  213. ixp4xx_exp_bus_size = SZ_16M;
  214. platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
  215. if (cpu_is_ixp46x()) {
  216. int region;
  217. platform_add_devices(ixp46x_devices,
  218. ARRAY_SIZE(ixp46x_devices));
  219. for (region = 0; region < 7; region++) {
  220. if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
  221. ixp4xx_exp_bus_size = SZ_32M;
  222. break;
  223. }
  224. }
  225. }
  226. printk("IXP4xx: Using %luMiB expansion bus window size\n",
  227. ixp4xx_exp_bus_size >> 20);
  228. }
  229. unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
  230. EXPORT_SYMBOL(ixp4xx_timer_freq);
  231. void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
  232. {
  233. if (mode == REBOOT_SOFT) {
  234. /* Jump into ROM at address 0 */
  235. soft_restart(0);
  236. } else {
  237. /* Use on-chip reset capability */
  238. /* set the "key" register to enable access to
  239. * "timer" and "enable" registers
  240. */
  241. *IXP4XX_OSWK = IXP4XX_WDT_KEY;
  242. /* write 0 to the timer register for an immediate reset */
  243. *IXP4XX_OSWT = 0;
  244. *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
  245. }
  246. }
  247. #ifdef CONFIG_PCI
  248. static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
  249. {
  250. return (dma_addr + size) > SZ_64M;
  251. }
  252. static int ixp4xx_platform_notify_remove(struct device *dev)
  253. {
  254. if (dev_is_pci(dev))
  255. dmabounce_unregister_dev(dev);
  256. return 0;
  257. }
  258. #endif
  259. /*
  260. * Setup DMA mask to 64MB on PCI devices and 4 GB on all other things.
  261. */
  262. static int ixp4xx_platform_notify(struct device *dev)
  263. {
  264. dev->dma_mask = &dev->coherent_dma_mask;
  265. #ifdef CONFIG_PCI
  266. if (dev_is_pci(dev)) {
  267. dev->coherent_dma_mask = DMA_BIT_MASK(28); /* 64 MB */
  268. dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
  269. return 0;
  270. }
  271. #endif
  272. dev->coherent_dma_mask = DMA_BIT_MASK(32);
  273. return 0;
  274. }
  275. int dma_set_coherent_mask(struct device *dev, u64 mask)
  276. {
  277. if (dev_is_pci(dev))
  278. mask &= DMA_BIT_MASK(28); /* 64 MB */
  279. if ((mask & DMA_BIT_MASK(28)) == DMA_BIT_MASK(28)) {
  280. dev->coherent_dma_mask = mask;
  281. return 0;
  282. }
  283. return -EIO; /* device wanted sub-64MB mask */
  284. }
  285. EXPORT_SYMBOL(dma_set_coherent_mask);
  286. #ifdef CONFIG_IXP4XX_INDIRECT_PCI
  287. /*
  288. * In the case of using indirect PCI, we simply return the actual PCI
  289. * address and our read/write implementation use that to drive the
  290. * access registers. If something outside of PCI is ioremap'd, we
  291. * fallback to the default.
  292. */
  293. static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
  294. unsigned int mtype, void *caller)
  295. {
  296. if (!is_pci_memory(addr))
  297. return __arm_ioremap_caller(addr, size, mtype, caller);
  298. return (void __iomem *)addr;
  299. }
  300. static void ixp4xx_iounmap(volatile void __iomem *addr)
  301. {
  302. if (!is_pci_memory((__force u32)addr))
  303. __iounmap(addr);
  304. }
  305. #endif
  306. void __init ixp4xx_init_early(void)
  307. {
  308. platform_notify = ixp4xx_platform_notify;
  309. #ifdef CONFIG_PCI
  310. platform_notify_remove = ixp4xx_platform_notify_remove;
  311. #endif
  312. #ifdef CONFIG_IXP4XX_INDIRECT_PCI
  313. arch_ioremap_caller = ixp4xx_ioremap_caller;
  314. arch_iounmap = ixp4xx_iounmap;
  315. #endif
  316. }