common-pci.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * arch/arm/mach-ixp4xx/common-pci.c
  4. *
  5. * IXP4XX PCI routines for all platforms
  6. *
  7. * Maintainer: Deepak Saxena <dsaxena@plexity.net>
  8. *
  9. * Copyright (C) 2002 Intel Corporation.
  10. * Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com>
  11. * Copyright (C) 2003-2004 MontaVista Software, Inc.
  12. */
  13. #include <linux/sched.h>
  14. #include <linux/kernel.h>
  15. #include <linux/pci.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/mm.h>
  18. #include <linux/init.h>
  19. #include <linux/ioport.h>
  20. #include <linux/slab.h>
  21. #include <linux/delay.h>
  22. #include <linux/device.h>
  23. #include <linux/io.h>
  24. #include <linux/export.h>
  25. #include <asm/dma-mapping.h>
  26. #include <asm/cputype.h>
  27. #include <asm/irq.h>
  28. #include <linux/sizes.h>
  29. #include <asm/mach/pci.h>
  30. #include <mach/hardware.h>
  31. /*
  32. * IXP4xx PCI read function is dependent on whether we are
  33. * running A0 or B0 (AppleGate) silicon.
  34. */
  35. int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
  36. /*
  37. * Base address for PCI register region
  38. */
  39. unsigned long ixp4xx_pci_reg_base = 0;
  40. /*
  41. * PCI cfg an I/O routines are done by programming a
  42. * command/byte enable register, and then read/writing
  43. * the data from a data register. We need to ensure
  44. * these transactions are atomic or we will end up
  45. * with corrupt data on the bus or in a driver.
  46. */
  47. static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock);
  48. /*
  49. * Read from PCI config space
  50. */
  51. static void crp_read(u32 ad_cbe, u32 *data)
  52. {
  53. unsigned long flags;
  54. raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
  55. *PCI_CRP_AD_CBE = ad_cbe;
  56. *data = *PCI_CRP_RDATA;
  57. raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
  58. }
  59. /*
  60. * Write to PCI config space
  61. */
  62. static void crp_write(u32 ad_cbe, u32 data)
  63. {
  64. unsigned long flags;
  65. raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
  66. *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
  67. *PCI_CRP_WDATA = data;
  68. raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
  69. }
  70. static inline int check_master_abort(void)
  71. {
  72. /* check Master Abort bit after access */
  73. unsigned long isr = *PCI_ISR;
  74. if (isr & PCI_ISR_PFE) {
  75. /* make sure the Master Abort bit is reset */
  76. *PCI_ISR = PCI_ISR_PFE;
  77. pr_debug("%s failed\n", __func__);
  78. return 1;
  79. }
  80. return 0;
  81. }
  82. int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
  83. {
  84. unsigned long flags;
  85. int retval = 0;
  86. int i;
  87. raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
  88. *PCI_NP_AD = addr;
  89. /*
  90. * PCI workaround - only works if NP PCI space reads have
  91. * no side effects!!! Read 8 times. last one will be good.
  92. */
  93. for (i = 0; i < 8; i++) {
  94. *PCI_NP_CBE = cmd;
  95. *data = *PCI_NP_RDATA;
  96. *data = *PCI_NP_RDATA;
  97. }
  98. if(check_master_abort())
  99. retval = 1;
  100. raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
  101. return retval;
  102. }
  103. int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
  104. {
  105. unsigned long flags;
  106. int retval = 0;
  107. raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
  108. *PCI_NP_AD = addr;
  109. /* set up and execute the read */
  110. *PCI_NP_CBE = cmd;
  111. /* the result of the read is now in NP_RDATA */
  112. *data = *PCI_NP_RDATA;
  113. if(check_master_abort())
  114. retval = 1;
  115. raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
  116. return retval;
  117. }
  118. int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
  119. {
  120. unsigned long flags;
  121. int retval = 0;
  122. raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
  123. *PCI_NP_AD = addr;
  124. /* set up the write */
  125. *PCI_NP_CBE = cmd;
  126. /* execute the write by writing to NP_WDATA */
  127. *PCI_NP_WDATA = data;
  128. if(check_master_abort())
  129. retval = 1;
  130. raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
  131. return retval;
  132. }
  133. static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
  134. {
  135. u32 addr;
  136. if (!bus_num) {
  137. /* type 0 */
  138. addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) |
  139. (where & ~3);
  140. } else {
  141. /* type 1 */
  142. addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) |
  143. ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
  144. }
  145. return addr;
  146. }
  147. /*
  148. * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
  149. * 0 and 3 are not valid indexes...
  150. */
  151. static u32 bytemask[] = {
  152. /*0*/ 0,
  153. /*1*/ 0xff,
  154. /*2*/ 0xffff,
  155. /*3*/ 0,
  156. /*4*/ 0xffffffff,
  157. };
  158. static u32 local_byte_lane_enable_bits(u32 n, int size)
  159. {
  160. if (size == 1)
  161. return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
  162. if (size == 2)
  163. return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
  164. if (size == 4)
  165. return 0;
  166. return 0xffffffff;
  167. }
  168. static int local_read_config(int where, int size, u32 *value)
  169. {
  170. u32 n, data;
  171. pr_debug("local_read_config from %d size %d\n", where, size);
  172. n = where % 4;
  173. crp_read(where & ~3, &data);
  174. *value = (data >> (8*n)) & bytemask[size];
  175. pr_debug("local_read_config read %#x\n", *value);
  176. return PCIBIOS_SUCCESSFUL;
  177. }
  178. static int local_write_config(int where, int size, u32 value)
  179. {
  180. u32 n, byte_enables, data;
  181. pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
  182. n = where % 4;
  183. byte_enables = local_byte_lane_enable_bits(n, size);
  184. if (byte_enables == 0xffffffff)
  185. return PCIBIOS_BAD_REGISTER_NUMBER;
  186. data = value << (8*n);
  187. crp_write((where & ~3) | byte_enables, data);
  188. return PCIBIOS_SUCCESSFUL;
  189. }
  190. static u32 byte_lane_enable_bits(u32 n, int size)
  191. {
  192. if (size == 1)
  193. return (0xf & ~BIT(n)) << 4;
  194. if (size == 2)
  195. return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
  196. if (size == 4)
  197. return 0;
  198. return 0xffffffff;
  199. }
  200. static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
  201. {
  202. u32 n, byte_enables, addr, data;
  203. u8 bus_num = bus->number;
  204. pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
  205. bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
  206. *value = 0xffffffff;
  207. n = where % 4;
  208. byte_enables = byte_lane_enable_bits(n, size);
  209. if (byte_enables == 0xffffffff)
  210. return PCIBIOS_BAD_REGISTER_NUMBER;
  211. addr = ixp4xx_config_addr(bus_num, devfn, where);
  212. if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data))
  213. return PCIBIOS_DEVICE_NOT_FOUND;
  214. *value = (data >> (8*n)) & bytemask[size];
  215. pr_debug("read_config_byte read %#x\n", *value);
  216. return PCIBIOS_SUCCESSFUL;
  217. }
  218. static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
  219. {
  220. u32 n, byte_enables, addr, data;
  221. u8 bus_num = bus->number;
  222. pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
  223. size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
  224. n = where % 4;
  225. byte_enables = byte_lane_enable_bits(n, size);
  226. if (byte_enables == 0xffffffff)
  227. return PCIBIOS_BAD_REGISTER_NUMBER;
  228. addr = ixp4xx_config_addr(bus_num, devfn, where);
  229. data = value << (8*n);
  230. if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data))
  231. return PCIBIOS_DEVICE_NOT_FOUND;
  232. return PCIBIOS_SUCCESSFUL;
  233. }
  234. struct pci_ops ixp4xx_ops = {
  235. .read = ixp4xx_pci_read_config,
  236. .write = ixp4xx_pci_write_config,
  237. };
  238. /*
  239. * PCI abort handler
  240. */
  241. static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
  242. {
  243. u32 isr, status;
  244. isr = *PCI_ISR;
  245. local_read_config(PCI_STATUS, 2, &status);
  246. pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
  247. "status = %#x\n", addr, isr, status);
  248. /* make sure the Master Abort bit is reset */
  249. *PCI_ISR = PCI_ISR_PFE;
  250. status |= PCI_STATUS_REC_MASTER_ABORT;
  251. local_write_config(PCI_STATUS, 2, status);
  252. /*
  253. * If it was an imprecise abort, then we need to correct the
  254. * return address to be _after_ the instruction.
  255. */
  256. if (fsr & (1 << 10))
  257. regs->ARM_pc += 4;
  258. return 0;
  259. }
  260. void __init ixp4xx_pci_preinit(void)
  261. {
  262. unsigned long cpuid = read_cpuid_id();
  263. #ifdef CONFIG_IXP4XX_INDIRECT_PCI
  264. pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */
  265. #else
  266. pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */
  267. #endif
  268. /*
  269. * Determine which PCI read method to use.
  270. * Rev 0 IXP425 requires workaround.
  271. */
  272. if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
  273. printk("PCI: IXP42x A0 silicon detected - "
  274. "PCI Non-Prefetch Workaround Enabled\n");
  275. ixp4xx_pci_read = ixp4xx_pci_read_errata;
  276. } else
  277. ixp4xx_pci_read = ixp4xx_pci_read_no_errata;
  278. /* hook in our fault handler for PCI errors */
  279. hook_fault_code(16+6, abort_handler, SIGBUS, 0,
  280. "imprecise external abort");
  281. pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
  282. /*
  283. * We use identity AHB->PCI address translation
  284. * in the 0x48000000 to 0x4bffffff address space
  285. */
  286. *PCI_PCIMEMBASE = 0x48494A4B;
  287. /*
  288. * We also use identity PCI->AHB address translation
  289. * in 4 16MB BARs that begin at the physical memory start
  290. */
  291. *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
  292. ((PHYS_OFFSET & 0xFF000000) >> 8) +
  293. ((PHYS_OFFSET & 0xFF000000) >> 16) +
  294. ((PHYS_OFFSET & 0xFF000000) >> 24) +
  295. 0x00010203;
  296. if (*PCI_CSR & PCI_CSR_HOST) {
  297. printk("PCI: IXP4xx is host\n");
  298. pr_debug("setup BARs in controller\n");
  299. /*
  300. * We configure the PCI inbound memory windows to be
  301. * 1:1 mapped to SDRAM
  302. */
  303. local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
  304. local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
  305. local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
  306. local_write_config(PCI_BASE_ADDRESS_3, 4,
  307. PHYS_OFFSET + SZ_32M + SZ_16M);
  308. /*
  309. * Enable CSR window at 64 MiB to allow PCI masters
  310. * to continue prefetching past 64 MiB boundary.
  311. */
  312. local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);
  313. /*
  314. * Enable the IO window to be way up high, at 0xfffffc00
  315. */
  316. local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
  317. local_write_config(0x40, 4, 0x000080FF); /* No TRDY time limit */
  318. } else {
  319. printk("PCI: IXP4xx is target - No bus scan performed\n");
  320. }
  321. printk("PCI: IXP4xx Using %s access for memory space\n",
  322. #ifndef CONFIG_IXP4XX_INDIRECT_PCI
  323. "direct"
  324. #else
  325. "indirect"
  326. #endif
  327. );
  328. pr_debug("clear error bits in ISR\n");
  329. *PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
  330. /*
  331. * Set Initialize Complete in PCI Control Register: allow IXP4XX to
  332. * respond to PCI configuration cycles. Specify that the AHB bus is
  333. * operating in big endian mode. Set up byte lane swapping between
  334. * little-endian PCI and the big-endian AHB bus
  335. */
  336. #ifdef __ARMEB__
  337. *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
  338. #else
  339. *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE;
  340. #endif
  341. pr_debug("DONE\n");
  342. }
  343. int ixp4xx_setup(int nr, struct pci_sys_data *sys)
  344. {
  345. struct resource *res;
  346. if (nr >= 1)
  347. return 0;
  348. res = kcalloc(2, sizeof(*res), GFP_KERNEL);
  349. if (res == NULL) {
  350. /*
  351. * If we're out of memory this early, something is wrong,
  352. * so we might as well catch it here.
  353. */
  354. panic("PCI: unable to allocate resources?\n");
  355. }
  356. local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
  357. res[0].name = "PCI I/O Space";
  358. res[0].start = 0x00000000;
  359. res[0].end = 0x0000ffff;
  360. res[0].flags = IORESOURCE_IO;
  361. res[1].name = "PCI Memory Space";
  362. res[1].start = PCIBIOS_MIN_MEM;
  363. res[1].end = PCIBIOS_MAX_MEM;
  364. res[1].flags = IORESOURCE_MEM;
  365. request_resource(&ioport_resource, &res[0]);
  366. request_resource(&iomem_resource, &res[1]);
  367. pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
  368. pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
  369. return 1;
  370. }
  371. EXPORT_SYMBOL(ixp4xx_pci_read);
  372. EXPORT_SYMBOL(ixp4xx_pci_write);