hardware.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * This file contains the hardware definitions of the Integrator.
  4. *
  5. * Copyright (C) 1998-1999 ARM Limited.
  6. */
  7. #ifndef INTEGRATOR_HARDWARE_H
  8. #define INTEGRATOR_HARDWARE_H
  9. /*
  10. * Where in virtual memory the IO devices (timers, system controllers
  11. * and so on)
  12. */
  13. #define IO_BASE 0xF0000000 // VA of IO
  14. #define IO_SIZE 0x0B000000 // How much?
  15. #define IO_START INTEGRATOR_HDR_BASE // PA of IO
  16. /* macro to get at IO space when running virtually */
  17. #ifdef CONFIG_MMU
  18. #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
  19. #else
  20. #define IO_ADDRESS(x) (x)
  21. #endif
  22. #define __io_address(n) ((void __iomem *)IO_ADDRESS(n))
  23. /*
  24. * Integrator memory map
  25. */
  26. #define INTEGRATOR_BOOT_ROM_LO 0x00000000
  27. #define INTEGRATOR_BOOT_ROM_HI 0x20000000
  28. #define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */
  29. #define INTEGRATOR_BOOT_ROM_SIZE SZ_512K
  30. /*
  31. * New Core Modules have different amounts of SSRAM, the amount of SSRAM
  32. * fitted can be found in HDR_STAT.
  33. *
  34. * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
  35. * the minimum amount of SSRAM fitted on any core module.
  36. *
  37. * New Core Modules also alias the SSRAM.
  38. *
  39. */
  40. #define INTEGRATOR_SSRAM_BASE 0x00000000
  41. #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
  42. #define INTEGRATOR_SSRAM_SIZE SZ_256K
  43. #define INTEGRATOR_FLASH_BASE 0x24000000
  44. #define INTEGRATOR_FLASH_SIZE SZ_32M
  45. #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
  46. #define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K
  47. /*
  48. * SDRAM is a SIMM therefore the size is not known.
  49. */
  50. #define INTEGRATOR_SDRAM_BASE 0x00040000
  51. #define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000
  52. #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
  53. #define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000
  54. #define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000
  55. #define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000
  56. /*
  57. * Logic expansion modules
  58. *
  59. */
  60. #define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000
  61. #define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000
  62. #define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000
  63. #define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000
  64. #define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000
  65. /*
  66. * Integrator header card registers
  67. */
  68. #define INTEGRATOR_HDR_ID_OFFSET 0x00
  69. #define INTEGRATOR_HDR_PROC_OFFSET 0x04
  70. #define INTEGRATOR_HDR_OSC_OFFSET 0x08
  71. #define INTEGRATOR_HDR_CTRL_OFFSET 0x0C
  72. #define INTEGRATOR_HDR_STAT_OFFSET 0x10
  73. #define INTEGRATOR_HDR_LOCK_OFFSET 0x14
  74. #define INTEGRATOR_HDR_SDRAM_OFFSET 0x20
  75. #define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */
  76. #define INTEGRATOR_HDR_IC_OFFSET 0x40
  77. #define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100
  78. #define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200
  79. #define INTEGRATOR_HDR_BASE 0x10000000
  80. #define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
  81. #define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
  82. #define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
  83. #define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
  84. #define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
  85. #define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
  86. #define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
  87. #define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
  88. #define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
  89. #define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
  90. #define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
  91. #define INTEGRATOR_HDR_CTRL_LED 0x01
  92. #define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
  93. #define INTEGRATOR_HDR_CTRL_REMAP 0x04
  94. #define INTEGRATOR_HDR_CTRL_RESET 0x08
  95. #define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
  96. #define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20
  97. #define INTEGRATOR_HDR_CTRL_FASTBUS 0x40
  98. #define INTEGRATOR_HDR_CTRL_SYNC 0x80
  99. #define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102
  100. #define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107
  101. #define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C
  102. #define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111
  103. #define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116
  104. #define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B
  105. #define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120
  106. #define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125
  107. #define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A
  108. #define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F
  109. #define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134
  110. #define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139
  111. #define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E
  112. #define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143
  113. #define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148
  114. #define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D
  115. #define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152
  116. #define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157
  117. #define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C
  118. #define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161
  119. #define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166
  120. #define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B
  121. #define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170
  122. #define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175
  123. #define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A
  124. #define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F
  125. #define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184
  126. #define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189
  127. #define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E
  128. #define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193
  129. #define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198
  130. #define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF
  131. #define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000
  132. #define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000
  133. #define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000
  134. #define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000
  135. #define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000
  136. #define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000
  137. #define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000
  138. #define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000
  139. #define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000
  140. #define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000
  141. #define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000
  142. #define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0
  143. #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000
  144. #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000
  145. #define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000
  146. #define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000
  147. #define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5)
  148. /*
  149. * Integrator system registers
  150. */
  151. /*
  152. * System Controller
  153. */
  154. #define INTEGRATOR_SC_ID_OFFSET 0x00
  155. #define INTEGRATOR_SC_OSC_OFFSET 0x04
  156. #define INTEGRATOR_SC_CTRLS_OFFSET 0x08
  157. #define INTEGRATOR_SC_CTRLC_OFFSET 0x0C
  158. #define INTEGRATOR_SC_DEC_OFFSET 0x10
  159. #define INTEGRATOR_SC_ARB_OFFSET 0x14
  160. #define INTEGRATOR_SC_LOCK_OFFSET 0x1C
  161. #define INTEGRATOR_SC_BASE 0x11000000
  162. #define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
  163. #define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
  164. #define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
  165. #define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
  166. #define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
  167. #define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
  168. #define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
  169. #define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
  170. #define INTEGRATOR_SC_OSC_SYS_10MHz 0x20
  171. #define INTEGRATOR_SC_OSC_SYS_15MHz 0x34
  172. #define INTEGRATOR_SC_OSC_SYS_20MHz 0x48
  173. #define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C
  174. #define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C
  175. #define INTEGRATOR_SC_OSC_SYS_MASK 0xFF
  176. #define INTEGRATOR_SC_OSC_PCI_25MHz 0x100
  177. #define INTEGRATOR_SC_OSC_PCI_33MHz 0x0
  178. #define INTEGRATOR_SC_OSC_PCI_MASK 0x100
  179. #define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0)
  180. #define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1)
  181. #define INTEGRATOR_SC_CTRL_nFLWP (1 << 2)
  182. #define INTEGRATOR_SC_CTRL_URTS0 (1 << 4)
  183. #define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5)
  184. #define INTEGRATOR_SC_CTRL_URTS1 (1 << 6)
  185. #define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7)
  186. /*
  187. * External Bus Interface
  188. */
  189. #define INTEGRATOR_EBI_BASE 0x12000000
  190. #define INTEGRATOR_EBI_CSR0_OFFSET 0x00
  191. #define INTEGRATOR_EBI_CSR1_OFFSET 0x04
  192. #define INTEGRATOR_EBI_CSR2_OFFSET 0x08
  193. #define INTEGRATOR_EBI_CSR3_OFFSET 0x0C
  194. #define INTEGRATOR_EBI_LOCK_OFFSET 0x20
  195. #define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
  196. #define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
  197. #define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
  198. #define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
  199. #define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
  200. #define INTEGRATOR_EBI_8_BIT 0x00
  201. #define INTEGRATOR_EBI_16_BIT 0x01
  202. #define INTEGRATOR_EBI_32_BIT 0x02
  203. #define INTEGRATOR_EBI_WRITE_ENABLE 0x04
  204. #define INTEGRATOR_EBI_SYNC 0x08
  205. #define INTEGRATOR_EBI_WS_2 0x00
  206. #define INTEGRATOR_EBI_WS_3 0x10
  207. #define INTEGRATOR_EBI_WS_4 0x20
  208. #define INTEGRATOR_EBI_WS_5 0x30
  209. #define INTEGRATOR_EBI_WS_6 0x40
  210. #define INTEGRATOR_EBI_WS_7 0x50
  211. #define INTEGRATOR_EBI_WS_8 0x60
  212. #define INTEGRATOR_EBI_WS_9 0x70
  213. #define INTEGRATOR_EBI_WS_10 0x80
  214. #define INTEGRATOR_EBI_WS_11 0x90
  215. #define INTEGRATOR_EBI_WS_12 0xA0
  216. #define INTEGRATOR_EBI_WS_13 0xB0
  217. #define INTEGRATOR_EBI_WS_14 0xC0
  218. #define INTEGRATOR_EBI_WS_15 0xD0
  219. #define INTEGRATOR_EBI_WS_16 0xE0
  220. #define INTEGRATOR_EBI_WS_17 0xF0
  221. #define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */
  222. #define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */
  223. #define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */
  224. #define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */
  225. #define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */
  226. #define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */
  227. #define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */
  228. /*
  229. * LED's & Switches
  230. */
  231. #define INTEGRATOR_DBG_ALPHA_OFFSET 0x00
  232. #define INTEGRATOR_DBG_LEDS_OFFSET 0x04
  233. #define INTEGRATOR_DBG_SWITCH_OFFSET 0x08
  234. #define INTEGRATOR_DBG_BASE 0x1A000000
  235. #define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
  236. #define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
  237. #define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
  238. #define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */
  239. #define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */
  240. #define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */
  241. #define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */
  242. #define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */
  243. #define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */
  244. #define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */
  245. /* PS2 Keyboard interface */
  246. #define KMI0_BASE INTEGRATOR_KBD_BASE
  247. /* PS2 Mouse interface */
  248. #define KMI1_BASE INTEGRATOR_MOUSE_BASE
  249. /*
  250. * Integrator Interrupt Controllers
  251. *
  252. *
  253. * Offsets from interrupt controller base
  254. *
  255. * System Controller interrupt controller base is
  256. *
  257. * INTEGRATOR_IC_BASE + (header_number << 6)
  258. *
  259. * Core Module interrupt controller base is
  260. *
  261. * INTEGRATOR_HDR_IC
  262. */
  263. #define IRQ_STATUS 0
  264. #define IRQ_RAW_STATUS 0x04
  265. #define IRQ_ENABLE 0x08
  266. #define IRQ_ENABLE_SET 0x08
  267. #define IRQ_ENABLE_CLEAR 0x0C
  268. #define INT_SOFT_SET 0x10
  269. #define INT_SOFT_CLEAR 0x14
  270. #define FIQ_STATUS 0x20
  271. #define FIQ_RAW_STATUS 0x24
  272. #define FIQ_ENABLE 0x28
  273. #define FIQ_ENABLE_SET 0x28
  274. #define FIQ_ENABLE_CLEAR 0x2C
  275. /*
  276. * LED's
  277. */
  278. #define GREEN_LED 0x01
  279. #define YELLOW_LED 0x02
  280. #define RED_LED 0x04
  281. #define GREEN_LED_2 0x08
  282. #define ALL_LEDS 0x0F
  283. #define LED_BANK INTEGRATOR_DBG_LEDS
  284. /*
  285. * Timer definitions
  286. *
  287. * Only use timer 1 & 2
  288. * (both run at 24MHz and will need the clock divider set to 16).
  289. *
  290. * Timer 0 runs at bus frequency
  291. */
  292. #define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
  293. #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
  294. #define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
  295. #define INTEGRATOR_CSR_BASE 0x10000000
  296. #define INTEGRATOR_CSR_SIZE 0x10000000
  297. #endif /* INTEGRATOR_HARDWARE_H */