platsmp.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 Linaro Ltd.
  4. * Copyright (c) 2013 Hisilicon Limited.
  5. * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
  6. */
  7. #include <linux/smp.h>
  8. #include <linux/io.h>
  9. #include <linux/of_address.h>
  10. #include <linux/delay.h>
  11. #include <asm/cacheflush.h>
  12. #include <asm/smp_plat.h>
  13. #include <asm/smp_scu.h>
  14. #include <asm/mach/map.h>
  15. #include "core.h"
  16. #define HIX5HD2_BOOT_ADDRESS 0xffff0000
  17. static void __iomem *ctrl_base;
  18. void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
  19. {
  20. cpu = cpu_logical_map(cpu);
  21. if (!cpu || !ctrl_base)
  22. return;
  23. writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2));
  24. }
  25. int hi3xxx_get_cpu_jump(int cpu)
  26. {
  27. cpu = cpu_logical_map(cpu);
  28. if (!cpu || !ctrl_base)
  29. return 0;
  30. return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
  31. }
  32. static void __init hisi_enable_scu_a9(void)
  33. {
  34. unsigned long base = 0;
  35. void __iomem *scu_base = NULL;
  36. if (scu_a9_has_base()) {
  37. base = scu_a9_get_base();
  38. scu_base = ioremap(base, SZ_4K);
  39. if (!scu_base) {
  40. pr_err("ioremap(scu_base) failed\n");
  41. return;
  42. }
  43. scu_enable(scu_base);
  44. iounmap(scu_base);
  45. }
  46. }
  47. static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
  48. {
  49. struct device_node *np = NULL;
  50. u32 offset = 0;
  51. hisi_enable_scu_a9();
  52. if (!ctrl_base) {
  53. np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
  54. if (!np) {
  55. pr_err("failed to find hisilicon,sysctrl node\n");
  56. return;
  57. }
  58. ctrl_base = of_iomap(np, 0);
  59. if (!ctrl_base) {
  60. pr_err("failed to map address\n");
  61. return;
  62. }
  63. if (of_property_read_u32(np, "smp-offset", &offset) < 0) {
  64. pr_err("failed to find smp-offset property\n");
  65. return;
  66. }
  67. ctrl_base += offset;
  68. }
  69. }
  70. static int hi3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle)
  71. {
  72. hi3xxx_set_cpu(cpu, true);
  73. hi3xxx_set_cpu_jump(cpu, secondary_startup);
  74. arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  75. return 0;
  76. }
  77. static const struct smp_operations hi3xxx_smp_ops __initconst = {
  78. .smp_prepare_cpus = hi3xxx_smp_prepare_cpus,
  79. .smp_boot_secondary = hi3xxx_boot_secondary,
  80. #ifdef CONFIG_HOTPLUG_CPU
  81. .cpu_die = hi3xxx_cpu_die,
  82. .cpu_kill = hi3xxx_cpu_kill,
  83. #endif
  84. };
  85. static void __init hisi_common_smp_prepare_cpus(unsigned int max_cpus)
  86. {
  87. hisi_enable_scu_a9();
  88. }
  89. static void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
  90. {
  91. void __iomem *virt;
  92. virt = ioremap(start_addr, PAGE_SIZE);
  93. writel_relaxed(0xe51ff004, virt); /* ldr pc, [pc, #-4] */
  94. writel_relaxed(jump_addr, virt + 4); /* pc jump phy address */
  95. iounmap(virt);
  96. }
  97. static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
  98. {
  99. phys_addr_t jumpaddr;
  100. jumpaddr = __pa_symbol(secondary_startup);
  101. hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
  102. hix5hd2_set_cpu(cpu, true);
  103. arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  104. return 0;
  105. }
  106. static const struct smp_operations hix5hd2_smp_ops __initconst = {
  107. .smp_prepare_cpus = hisi_common_smp_prepare_cpus,
  108. .smp_boot_secondary = hix5hd2_boot_secondary,
  109. #ifdef CONFIG_HOTPLUG_CPU
  110. .cpu_die = hix5hd2_cpu_die,
  111. #endif
  112. };
  113. #define SC_SCTL_REMAP_CLR 0x00000100
  114. #define HIP01_BOOT_ADDRESS 0x80000000
  115. #define REG_SC_CTRL 0x000
  116. static void hip01_set_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
  117. {
  118. void __iomem *virt;
  119. virt = phys_to_virt(start_addr);
  120. writel_relaxed(0xe51ff004, virt);
  121. writel_relaxed(jump_addr, virt + 4);
  122. }
  123. static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
  124. {
  125. phys_addr_t jumpaddr;
  126. unsigned int remap_reg_value = 0;
  127. struct device_node *node;
  128. jumpaddr = __pa_symbol(secondary_startup);
  129. hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
  130. node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
  131. if (WARN_ON(!node))
  132. return -1;
  133. ctrl_base = of_iomap(node, 0);
  134. /* set the secondary core boot from DDR */
  135. remap_reg_value = readl_relaxed(ctrl_base + REG_SC_CTRL);
  136. barrier();
  137. remap_reg_value |= SC_SCTL_REMAP_CLR;
  138. barrier();
  139. writel_relaxed(remap_reg_value, ctrl_base + REG_SC_CTRL);
  140. hip01_set_cpu(cpu, true);
  141. return 0;
  142. }
  143. static const struct smp_operations hip01_smp_ops __initconst = {
  144. .smp_prepare_cpus = hisi_common_smp_prepare_cpus,
  145. .smp_boot_secondary = hip01_boot_secondary,
  146. };
  147. CPU_METHOD_OF_DECLARE(hi3xxx_smp, "hisilicon,hi3620-smp", &hi3xxx_smp_ops);
  148. CPU_METHOD_OF_DECLARE(hix5hd2_smp, "hisilicon,hix5hd2-smp", &hix5hd2_smp_ops);
  149. CPU_METHOD_OF_DECLARE(hip01_smp, "hisilicon,hip01-smp", &hip01_smp_ops);