platmcpm.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013-2014 Linaro Ltd.
  4. * Copyright (c) 2013-2014 Hisilicon Limited.
  5. */
  6. #include <linux/init.h>
  7. #include <linux/smp.h>
  8. #include <linux/delay.h>
  9. #include <linux/io.h>
  10. #include <linux/memblock.h>
  11. #include <linux/of_address.h>
  12. #include <asm/cputype.h>
  13. #include <asm/cp15.h>
  14. #include <asm/cacheflush.h>
  15. #include <asm/smp.h>
  16. #include <asm/smp_plat.h>
  17. #include "core.h"
  18. /* bits definition in SC_CPU_RESET_REQ[x]/SC_CPU_RESET_DREQ[x]
  19. * 1 -- unreset; 0 -- reset
  20. */
  21. #define CORE_RESET_BIT(x) (1 << x)
  22. #define NEON_RESET_BIT(x) (1 << (x + 4))
  23. #define CORE_DEBUG_RESET_BIT(x) (1 << (x + 9))
  24. #define CLUSTER_L2_RESET_BIT (1 << 8)
  25. #define CLUSTER_DEBUG_RESET_BIT (1 << 13)
  26. /*
  27. * bits definition in SC_CPU_RESET_STATUS[x]
  28. * 1 -- reset status; 0 -- unreset status
  29. */
  30. #define CORE_RESET_STATUS(x) (1 << x)
  31. #define NEON_RESET_STATUS(x) (1 << (x + 4))
  32. #define CORE_DEBUG_RESET_STATUS(x) (1 << (x + 9))
  33. #define CLUSTER_L2_RESET_STATUS (1 << 8)
  34. #define CLUSTER_DEBUG_RESET_STATUS (1 << 13)
  35. #define CORE_WFI_STATUS(x) (1 << (x + 16))
  36. #define CORE_WFE_STATUS(x) (1 << (x + 20))
  37. #define CORE_DEBUG_ACK(x) (1 << (x + 24))
  38. #define SC_CPU_RESET_REQ(x) (0x520 + (x << 3)) /* reset */
  39. #define SC_CPU_RESET_DREQ(x) (0x524 + (x << 3)) /* unreset */
  40. #define SC_CPU_RESET_STATUS(x) (0x1520 + (x << 3))
  41. #define FAB_SF_MODE 0x0c
  42. #define FAB_SF_INVLD 0x10
  43. /* bits definition in FB_SF_INVLD */
  44. #define FB_SF_INVLD_START (1 << 8)
  45. #define HIP04_MAX_CLUSTERS 4
  46. #define HIP04_MAX_CPUS_PER_CLUSTER 4
  47. #define POLL_MSEC 10
  48. #define TIMEOUT_MSEC 1000
  49. static void __iomem *sysctrl, *fabric;
  50. static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
  51. static DEFINE_SPINLOCK(boot_lock);
  52. static u32 fabric_phys_addr;
  53. /*
  54. * [0]: bootwrapper physical address
  55. * [1]: bootwrapper size
  56. * [2]: relocation address
  57. * [3]: relocation size
  58. */
  59. static u32 hip04_boot_method[4];
  60. static bool hip04_cluster_is_down(unsigned int cluster)
  61. {
  62. int i;
  63. for (i = 0; i < HIP04_MAX_CPUS_PER_CLUSTER; i++)
  64. if (hip04_cpu_table[cluster][i])
  65. return false;
  66. return true;
  67. }
  68. static void hip04_set_snoop_filter(unsigned int cluster, unsigned int on)
  69. {
  70. unsigned long data;
  71. if (!fabric)
  72. BUG();
  73. data = readl_relaxed(fabric + FAB_SF_MODE);
  74. if (on)
  75. data |= 1 << cluster;
  76. else
  77. data &= ~(1 << cluster);
  78. writel_relaxed(data, fabric + FAB_SF_MODE);
  79. do {
  80. cpu_relax();
  81. } while (data != readl_relaxed(fabric + FAB_SF_MODE));
  82. }
  83. static int hip04_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
  84. {
  85. unsigned int mpidr, cpu, cluster;
  86. unsigned long data;
  87. void __iomem *sys_dreq, *sys_status;
  88. mpidr = cpu_logical_map(l_cpu);
  89. cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
  90. cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
  91. if (!sysctrl)
  92. return -ENODEV;
  93. if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
  94. return -EINVAL;
  95. spin_lock_irq(&boot_lock);
  96. if (hip04_cpu_table[cluster][cpu])
  97. goto out;
  98. sys_dreq = sysctrl + SC_CPU_RESET_DREQ(cluster);
  99. sys_status = sysctrl + SC_CPU_RESET_STATUS(cluster);
  100. if (hip04_cluster_is_down(cluster)) {
  101. data = CLUSTER_DEBUG_RESET_BIT;
  102. writel_relaxed(data, sys_dreq);
  103. do {
  104. cpu_relax();
  105. data = readl_relaxed(sys_status);
  106. } while (data & CLUSTER_DEBUG_RESET_STATUS);
  107. hip04_set_snoop_filter(cluster, 1);
  108. }
  109. data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
  110. CORE_DEBUG_RESET_BIT(cpu);
  111. writel_relaxed(data, sys_dreq);
  112. do {
  113. cpu_relax();
  114. } while (data == readl_relaxed(sys_status));
  115. /*
  116. * We may fail to power up core again without this delay.
  117. * It's not mentioned in document. It's found by test.
  118. */
  119. udelay(20);
  120. arch_send_wakeup_ipi_mask(cpumask_of(l_cpu));
  121. out:
  122. hip04_cpu_table[cluster][cpu]++;
  123. spin_unlock_irq(&boot_lock);
  124. return 0;
  125. }
  126. #ifdef CONFIG_HOTPLUG_CPU
  127. static void hip04_cpu_die(unsigned int l_cpu)
  128. {
  129. unsigned int mpidr, cpu, cluster;
  130. bool last_man;
  131. mpidr = cpu_logical_map(l_cpu);
  132. cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
  133. cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
  134. spin_lock(&boot_lock);
  135. hip04_cpu_table[cluster][cpu]--;
  136. if (hip04_cpu_table[cluster][cpu] == 1) {
  137. /* A power_up request went ahead of us. */
  138. spin_unlock(&boot_lock);
  139. return;
  140. } else if (hip04_cpu_table[cluster][cpu] > 1) {
  141. pr_err("Cluster %d CPU%d boots multiple times\n", cluster, cpu);
  142. BUG();
  143. }
  144. last_man = hip04_cluster_is_down(cluster);
  145. spin_unlock(&boot_lock);
  146. if (last_man) {
  147. /* Since it's Cortex A15, disable L2 prefetching. */
  148. asm volatile(
  149. "mcr p15, 1, %0, c15, c0, 3 \n\t"
  150. "isb \n\t"
  151. "dsb "
  152. : : "r" (0x400) );
  153. v7_exit_coherency_flush(all);
  154. } else {
  155. v7_exit_coherency_flush(louis);
  156. }
  157. for (;;)
  158. wfi();
  159. }
  160. static int hip04_cpu_kill(unsigned int l_cpu)
  161. {
  162. unsigned int mpidr, cpu, cluster;
  163. unsigned int data, tries, count;
  164. mpidr = cpu_logical_map(l_cpu);
  165. cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
  166. cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
  167. BUG_ON(cluster >= HIP04_MAX_CLUSTERS ||
  168. cpu >= HIP04_MAX_CPUS_PER_CLUSTER);
  169. count = TIMEOUT_MSEC / POLL_MSEC;
  170. spin_lock_irq(&boot_lock);
  171. for (tries = 0; tries < count; tries++) {
  172. if (hip04_cpu_table[cluster][cpu])
  173. goto err;
  174. cpu_relax();
  175. data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
  176. if (data & CORE_WFI_STATUS(cpu))
  177. break;
  178. spin_unlock_irq(&boot_lock);
  179. /* Wait for clean L2 when the whole cluster is down. */
  180. msleep(POLL_MSEC);
  181. spin_lock_irq(&boot_lock);
  182. }
  183. if (tries >= count)
  184. goto err;
  185. data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
  186. CORE_DEBUG_RESET_BIT(cpu);
  187. writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster));
  188. for (tries = 0; tries < count; tries++) {
  189. cpu_relax();
  190. data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
  191. if (data & CORE_RESET_STATUS(cpu))
  192. break;
  193. }
  194. if (tries >= count)
  195. goto err;
  196. if (hip04_cluster_is_down(cluster))
  197. hip04_set_snoop_filter(cluster, 0);
  198. spin_unlock_irq(&boot_lock);
  199. return 1;
  200. err:
  201. spin_unlock_irq(&boot_lock);
  202. return 0;
  203. }
  204. #endif
  205. static const struct smp_operations hip04_smp_ops __initconst = {
  206. .smp_boot_secondary = hip04_boot_secondary,
  207. #ifdef CONFIG_HOTPLUG_CPU
  208. .cpu_die = hip04_cpu_die,
  209. .cpu_kill = hip04_cpu_kill,
  210. #endif
  211. };
  212. static bool __init hip04_cpu_table_init(void)
  213. {
  214. unsigned int mpidr, cpu, cluster;
  215. mpidr = read_cpuid_mpidr();
  216. cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
  217. cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
  218. if (cluster >= HIP04_MAX_CLUSTERS ||
  219. cpu >= HIP04_MAX_CPUS_PER_CLUSTER) {
  220. pr_err("%s: boot CPU is out of bound!\n", __func__);
  221. return false;
  222. }
  223. hip04_set_snoop_filter(cluster, 1);
  224. hip04_cpu_table[cluster][cpu] = 1;
  225. return true;
  226. }
  227. static int __init hip04_smp_init(void)
  228. {
  229. struct device_node *np, *np_sctl, *np_fab;
  230. struct resource fab_res;
  231. void __iomem *relocation;
  232. int ret = -ENODEV;
  233. np = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-bootwrapper");
  234. if (!np)
  235. goto err;
  236. ret = of_property_read_u32_array(np, "boot-method",
  237. &hip04_boot_method[0], 4);
  238. if (ret)
  239. goto err;
  240. ret = -ENODEV;
  241. np_sctl = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
  242. if (!np_sctl)
  243. goto err;
  244. np_fab = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-fabric");
  245. if (!np_fab)
  246. goto err;
  247. ret = memblock_reserve(hip04_boot_method[0], hip04_boot_method[1]);
  248. if (ret)
  249. goto err;
  250. relocation = ioremap(hip04_boot_method[2], hip04_boot_method[3]);
  251. if (!relocation) {
  252. pr_err("failed to map relocation space\n");
  253. ret = -ENOMEM;
  254. goto err_reloc;
  255. }
  256. sysctrl = of_iomap(np_sctl, 0);
  257. if (!sysctrl) {
  258. pr_err("failed to get sysctrl base\n");
  259. ret = -ENOMEM;
  260. goto err_sysctrl;
  261. }
  262. ret = of_address_to_resource(np_fab, 0, &fab_res);
  263. if (ret) {
  264. pr_err("failed to get fabric base phys\n");
  265. goto err_fabric;
  266. }
  267. fabric_phys_addr = fab_res.start;
  268. sync_cache_w(&fabric_phys_addr);
  269. fabric = of_iomap(np_fab, 0);
  270. if (!fabric) {
  271. pr_err("failed to get fabric base\n");
  272. ret = -ENOMEM;
  273. goto err_fabric;
  274. }
  275. if (!hip04_cpu_table_init()) {
  276. ret = -EINVAL;
  277. goto err_table;
  278. }
  279. /*
  280. * Fill the instruction address that is used after secondary core
  281. * out of reset.
  282. */
  283. writel_relaxed(hip04_boot_method[0], relocation);
  284. writel_relaxed(0xa5a5a5a5, relocation + 4); /* magic number */
  285. writel_relaxed(__pa_symbol(secondary_startup), relocation + 8);
  286. writel_relaxed(0, relocation + 12);
  287. iounmap(relocation);
  288. smp_set_ops(&hip04_smp_ops);
  289. return ret;
  290. err_table:
  291. iounmap(fabric);
  292. err_fabric:
  293. iounmap(sysctrl);
  294. err_sysctrl:
  295. iounmap(relocation);
  296. err_reloc:
  297. memblock_free(hip04_boot_method[0], hip04_boot_method[1]);
  298. err:
  299. return ret;
  300. }
  301. early_initcall(hip04_smp_init);