hotplug.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 Linaro Ltd.
  4. * Copyright (c) 2013 Hisilicon Limited.
  5. */
  6. #include <linux/cpu.h>
  7. #include <linux/delay.h>
  8. #include <linux/io.h>
  9. #include <linux/of_address.h>
  10. #include <linux/of_platform.h>
  11. #include <asm/cacheflush.h>
  12. #include <asm/smp_plat.h>
  13. #include "core.h"
  14. /* Sysctrl registers in Hi3620 SoC */
  15. #define SCISOEN 0xc0
  16. #define SCISODIS 0xc4
  17. #define SCPERPWREN 0xd0
  18. #define SCPERPWRDIS 0xd4
  19. #define SCCPUCOREEN 0xf4
  20. #define SCCPUCOREDIS 0xf8
  21. #define SCPERCTRL0 0x200
  22. #define SCCPURSTEN 0x410
  23. #define SCCPURSTDIS 0x414
  24. /*
  25. * bit definition in SCISOEN/SCPERPWREN/...
  26. *
  27. * CPU2_ISO_CTRL (1 << 5)
  28. * CPU3_ISO_CTRL (1 << 6)
  29. * ...
  30. */
  31. #define CPU2_ISO_CTRL (1 << 5)
  32. /*
  33. * bit definition in SCPERCTRL0
  34. *
  35. * CPU0_WFI_MASK_CFG (1 << 28)
  36. * CPU1_WFI_MASK_CFG (1 << 29)
  37. * ...
  38. */
  39. #define CPU0_WFI_MASK_CFG (1 << 28)
  40. /*
  41. * bit definition in SCCPURSTEN/...
  42. *
  43. * CPU0_SRST_REQ_EN (1 << 0)
  44. * CPU1_SRST_REQ_EN (1 << 1)
  45. * ...
  46. */
  47. #define CPU0_HPM_SRST_REQ_EN (1 << 22)
  48. #define CPU0_DBG_SRST_REQ_EN (1 << 12)
  49. #define CPU0_NEON_SRST_REQ_EN (1 << 4)
  50. #define CPU0_SRST_REQ_EN (1 << 0)
  51. #define HIX5HD2_PERI_CRG20 0x50
  52. #define CRG20_CPU1_RESET (1 << 17)
  53. #define HIX5HD2_PERI_PMC0 0x1000
  54. #define PMC0_CPU1_WAIT_MTCOMS_ACK (1 << 8)
  55. #define PMC0_CPU1_PMC_ENABLE (1 << 7)
  56. #define PMC0_CPU1_POWERDOWN (1 << 3)
  57. #define HIP01_PERI9 0x50
  58. #define PERI9_CPU1_RESET (1 << 1)
  59. enum {
  60. HI3620_CTRL,
  61. ERROR_CTRL,
  62. };
  63. static void __iomem *ctrl_base;
  64. static int id;
  65. static void set_cpu_hi3620(int cpu, bool enable)
  66. {
  67. u32 val = 0;
  68. if (enable) {
  69. /* MTCMOS set */
  70. if ((cpu == 2) || (cpu == 3))
  71. writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
  72. ctrl_base + SCPERPWREN);
  73. udelay(100);
  74. /* Enable core */
  75. writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);
  76. /* unreset */
  77. val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
  78. | CPU0_SRST_REQ_EN;
  79. writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
  80. /* reset */
  81. val |= CPU0_HPM_SRST_REQ_EN;
  82. writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
  83. /* ISO disable */
  84. if ((cpu == 2) || (cpu == 3))
  85. writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
  86. ctrl_base + SCISODIS);
  87. udelay(1);
  88. /* WFI Mask */
  89. val = readl_relaxed(ctrl_base + SCPERCTRL0);
  90. val &= ~(CPU0_WFI_MASK_CFG << cpu);
  91. writel_relaxed(val, ctrl_base + SCPERCTRL0);
  92. /* Unreset */
  93. val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
  94. | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
  95. writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
  96. } else {
  97. /* wfi mask */
  98. val = readl_relaxed(ctrl_base + SCPERCTRL0);
  99. val |= (CPU0_WFI_MASK_CFG << cpu);
  100. writel_relaxed(val, ctrl_base + SCPERCTRL0);
  101. /* disable core*/
  102. writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);
  103. if ((cpu == 2) || (cpu == 3)) {
  104. /* iso enable */
  105. writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
  106. ctrl_base + SCISOEN);
  107. udelay(1);
  108. }
  109. /* reset */
  110. val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
  111. | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
  112. writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
  113. if ((cpu == 2) || (cpu == 3)) {
  114. /* MTCMOS unset */
  115. writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
  116. ctrl_base + SCPERPWRDIS);
  117. udelay(100);
  118. }
  119. }
  120. }
  121. static int hi3xxx_hotplug_init(void)
  122. {
  123. struct device_node *node;
  124. node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
  125. if (!node) {
  126. id = ERROR_CTRL;
  127. return -ENOENT;
  128. }
  129. ctrl_base = of_iomap(node, 0);
  130. of_node_put(node);
  131. if (!ctrl_base) {
  132. id = ERROR_CTRL;
  133. return -ENOMEM;
  134. }
  135. id = HI3620_CTRL;
  136. return 0;
  137. }
  138. void hi3xxx_set_cpu(int cpu, bool enable)
  139. {
  140. if (!ctrl_base) {
  141. if (hi3xxx_hotplug_init() < 0)
  142. return;
  143. }
  144. if (id == HI3620_CTRL)
  145. set_cpu_hi3620(cpu, enable);
  146. }
  147. static bool hix5hd2_hotplug_init(void)
  148. {
  149. struct device_node *np;
  150. np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl");
  151. if (!np)
  152. return false;
  153. ctrl_base = of_iomap(np, 0);
  154. of_node_put(np);
  155. if (!ctrl_base)
  156. return false;
  157. return true;
  158. }
  159. void hix5hd2_set_cpu(int cpu, bool enable)
  160. {
  161. u32 val = 0;
  162. if (!ctrl_base)
  163. if (!hix5hd2_hotplug_init())
  164. BUG();
  165. if (enable) {
  166. /* power on cpu1 */
  167. val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
  168. val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN);
  169. val |= PMC0_CPU1_PMC_ENABLE;
  170. writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
  171. /* unreset */
  172. val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
  173. val &= ~CRG20_CPU1_RESET;
  174. writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
  175. } else {
  176. /* power down cpu1 */
  177. val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
  178. val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN;
  179. val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK;
  180. writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
  181. /* reset */
  182. val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
  183. val |= CRG20_CPU1_RESET;
  184. writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
  185. }
  186. }
  187. void hip01_set_cpu(int cpu, bool enable)
  188. {
  189. unsigned int temp;
  190. struct device_node *np;
  191. if (!ctrl_base) {
  192. np = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
  193. BUG_ON(!np);
  194. ctrl_base = of_iomap(np, 0);
  195. of_node_put(np);
  196. BUG_ON(!ctrl_base);
  197. }
  198. if (enable) {
  199. /* reset on CPU1 */
  200. temp = readl_relaxed(ctrl_base + HIP01_PERI9);
  201. temp |= PERI9_CPU1_RESET;
  202. writel_relaxed(temp, ctrl_base + HIP01_PERI9);
  203. udelay(50);
  204. /* unreset on CPU1 */
  205. temp = readl_relaxed(ctrl_base + HIP01_PERI9);
  206. temp &= ~PERI9_CPU1_RESET;
  207. writel_relaxed(temp, ctrl_base + HIP01_PERI9);
  208. }
  209. }
  210. static inline void cpu_enter_lowpower(void)
  211. {
  212. unsigned int v;
  213. flush_cache_all();
  214. /*
  215. * Turn off coherency and L1 D-cache
  216. */
  217. asm volatile(
  218. " mrc p15, 0, %0, c1, c0, 1\n"
  219. " bic %0, %0, #0x40\n"
  220. " mcr p15, 0, %0, c1, c0, 1\n"
  221. " mrc p15, 0, %0, c1, c0, 0\n"
  222. " bic %0, %0, #0x04\n"
  223. " mcr p15, 0, %0, c1, c0, 0\n"
  224. : "=&r" (v)
  225. : "r" (0)
  226. : "cc");
  227. }
  228. #ifdef CONFIG_HOTPLUG_CPU
  229. void hi3xxx_cpu_die(unsigned int cpu)
  230. {
  231. cpu_enter_lowpower();
  232. hi3xxx_set_cpu_jump(cpu, phys_to_virt(0));
  233. cpu_do_idle();
  234. /* We should have never returned from idle */
  235. panic("cpu %d unexpectedly exit from shutdown\n", cpu);
  236. }
  237. int hi3xxx_cpu_kill(unsigned int cpu)
  238. {
  239. unsigned long timeout = jiffies + msecs_to_jiffies(50);
  240. while (hi3xxx_get_cpu_jump(cpu))
  241. if (time_after(jiffies, timeout))
  242. return 0;
  243. hi3xxx_set_cpu(cpu, false);
  244. return 1;
  245. }
  246. void hix5hd2_cpu_die(unsigned int cpu)
  247. {
  248. flush_cache_all();
  249. hix5hd2_set_cpu(cpu, false);
  250. }
  251. #endif