timer-ep93xx.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/clocksource.h>
  5. #include <linux/clockchips.h>
  6. #include <linux/sched_clock.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/irq.h>
  9. #include <linux/io.h>
  10. #include <asm/mach/time.h>
  11. #include "soc.h"
  12. /*************************************************************************
  13. * Timer handling for EP93xx
  14. *************************************************************************
  15. * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
  16. * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
  17. * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
  18. * is free-running, and can't generate interrupts.
  19. *
  20. * The 508 kHz timers are ideal for use for the timer interrupt, as the
  21. * most common values of HZ divide 508 kHz nicely. We pick the 32 bit
  22. * timer (timer 3) to get as long sleep intervals as possible when using
  23. * CONFIG_NO_HZ.
  24. *
  25. * The higher clock rate of timer 4 makes it a better choice than the
  26. * other timers for use as clock source and for sched_clock(), providing
  27. * a stable 40 bit time base.
  28. *************************************************************************
  29. */
  30. #define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
  31. #define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
  32. #define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
  33. #define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
  34. #define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
  35. #define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
  36. #define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
  37. #define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
  38. #define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
  39. #define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
  40. #define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
  41. #define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
  42. #define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
  43. #define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
  44. #define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
  45. #define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
  46. #define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
  47. #define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
  48. #define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
  49. #define EP93XX_TIMER123_RATE 508469
  50. #define EP93XX_TIMER4_RATE 983040
  51. static u64 notrace ep93xx_read_sched_clock(void)
  52. {
  53. u64 ret;
  54. ret = readl(EP93XX_TIMER4_VALUE_LOW);
  55. ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
  56. return ret;
  57. }
  58. u64 ep93xx_clocksource_read(struct clocksource *c)
  59. {
  60. u64 ret;
  61. ret = readl(EP93XX_TIMER4_VALUE_LOW);
  62. ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
  63. return (u64) ret;
  64. }
  65. static int ep93xx_clkevt_set_next_event(unsigned long next,
  66. struct clock_event_device *evt)
  67. {
  68. /* Default mode: periodic, off, 508 kHz */
  69. u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
  70. EP93XX_TIMER123_CONTROL_CLKSEL;
  71. /* Clear timer */
  72. writel(tmode, EP93XX_TIMER3_CONTROL);
  73. /* Set next event */
  74. writel(next, EP93XX_TIMER3_LOAD);
  75. writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
  76. EP93XX_TIMER3_CONTROL);
  77. return 0;
  78. }
  79. static int ep93xx_clkevt_shutdown(struct clock_event_device *evt)
  80. {
  81. /* Disable timer */
  82. writel(0, EP93XX_TIMER3_CONTROL);
  83. return 0;
  84. }
  85. static struct clock_event_device ep93xx_clockevent = {
  86. .name = "timer1",
  87. .features = CLOCK_EVT_FEAT_ONESHOT,
  88. .set_state_shutdown = ep93xx_clkevt_shutdown,
  89. .set_state_oneshot = ep93xx_clkevt_shutdown,
  90. .tick_resume = ep93xx_clkevt_shutdown,
  91. .set_next_event = ep93xx_clkevt_set_next_event,
  92. .rating = 300,
  93. };
  94. static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
  95. {
  96. struct clock_event_device *evt = dev_id;
  97. /* Writing any value clears the timer interrupt */
  98. writel(1, EP93XX_TIMER3_CLEAR);
  99. evt->event_handler(evt);
  100. return IRQ_HANDLED;
  101. }
  102. void __init ep93xx_timer_init(void)
  103. {
  104. int irq = IRQ_EP93XX_TIMER3;
  105. unsigned long flags = IRQF_TIMER | IRQF_IRQPOLL;
  106. /* Enable and register clocksource and sched_clock on timer 4 */
  107. writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
  108. EP93XX_TIMER4_VALUE_HIGH);
  109. clocksource_mmio_init(NULL, "timer4",
  110. EP93XX_TIMER4_RATE, 200, 40,
  111. ep93xx_clocksource_read);
  112. sched_clock_register(ep93xx_read_sched_clock, 40,
  113. EP93XX_TIMER4_RATE);
  114. /* Set up clockevent on timer 3 */
  115. if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer",
  116. &ep93xx_clockevent))
  117. pr_err("Failed to request irq %d (ep93xx timer)\n", irq);
  118. clockevents_config_and_register(&ep93xx_clockevent,
  119. EP93XX_TIMER123_RATE,
  120. 1,
  121. 0xffffffffU);
  122. }