io.c 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/arm/mach-ebsa110/isamem.c
  4. *
  5. * Copyright (C) 2001 Russell King
  6. *
  7. * Perform "ISA" memory and IO accesses. The EBSA110 has some "peculiarities"
  8. * in the way it handles accesses to odd IO ports on 16-bit devices. These
  9. * devices have their D0-D15 lines connected to the processors D0-D15 lines.
  10. * Since they expect all byte IO operations to be performed on D0-D7, and the
  11. * StrongARM expects to transfer the byte to these odd addresses on D8-D15,
  12. * we must use a trick to get the required behaviour.
  13. *
  14. * The trick employed here is to use long word stores to odd address -1. The
  15. * glue logic picks this up as a "trick" access, and asserts the LSB of the
  16. * peripherals address bus, thereby accessing the odd IO port. Meanwhile, the
  17. * StrongARM transfers its data on D0-D7 as expected.
  18. *
  19. * Things get more interesting on the pass-1 EBSA110 - the PCMCIA controller
  20. * wiring was screwed in such a way that it had limited memory space access.
  21. * Luckily, the work-around for this is not too horrible. See
  22. * __isamem_convert_addr for the details.
  23. */
  24. #include <linux/module.h>
  25. #include <linux/kernel.h>
  26. #include <linux/types.h>
  27. #include <linux/io.h>
  28. #include <mach/hardware.h>
  29. #include <asm/page.h>
  30. static void __iomem *__isamem_convert_addr(const volatile void __iomem *addr)
  31. {
  32. u32 ret, a = (u32 __force) addr;
  33. /*
  34. * The PCMCIA controller is wired up as follows:
  35. * +---------+---------+---------+---------+---------+---------+
  36. * PCMCIA | 2 2 2 2 | 1 1 1 1 | 1 1 1 1 | 1 1 | | |
  37. * | 3 2 1 0 | 9 8 7 6 | 5 4 3 2 | 1 0 9 8 | 7 6 5 4 | 3 2 1 0 |
  38. * +---------+---------+---------+---------+---------+---------+
  39. * CPU | 2 2 2 2 | 2 1 1 1 | 1 1 1 1 | 1 1 1 | | |
  40. * | 4 3 2 1 | 0 9 9 8 | 7 6 5 4 | 3 2 0 9 | 8 7 6 5 | 4 3 2 x |
  41. * +---------+---------+---------+---------+---------+---------+
  42. *
  43. * This means that we can access PCMCIA regions as follows:
  44. * 0x*10000 -> 0x*1ffff
  45. * 0x*70000 -> 0x*7ffff
  46. * 0x*90000 -> 0x*9ffff
  47. * 0x*f0000 -> 0x*fffff
  48. */
  49. ret = (a & 0xf803fe) << 1;
  50. ret |= (a & 0x03fc00) << 2;
  51. ret += 0xe8000000;
  52. if ((a & 0x20000) == (a & 0x40000) >> 1)
  53. return (void __iomem *)ret;
  54. BUG();
  55. return NULL;
  56. }
  57. /*
  58. * read[bwl] and write[bwl]
  59. */
  60. u8 __readb(const volatile void __iomem *addr)
  61. {
  62. void __iomem *a = __isamem_convert_addr(addr);
  63. u32 ret;
  64. if ((unsigned long)addr & 1)
  65. ret = __raw_readl(a);
  66. else
  67. ret = __raw_readb(a);
  68. return ret;
  69. }
  70. u16 __readw(const volatile void __iomem *addr)
  71. {
  72. void __iomem *a = __isamem_convert_addr(addr);
  73. if ((unsigned long)addr & 1)
  74. BUG();
  75. return __raw_readw(a);
  76. }
  77. u32 __readl(const volatile void __iomem *addr)
  78. {
  79. void __iomem *a = __isamem_convert_addr(addr);
  80. u32 ret;
  81. if ((unsigned long)addr & 3)
  82. BUG();
  83. ret = __raw_readw(a);
  84. ret |= __raw_readw(a + 4) << 16;
  85. return ret;
  86. }
  87. EXPORT_SYMBOL(__readb);
  88. EXPORT_SYMBOL(__readw);
  89. EXPORT_SYMBOL(__readl);
  90. void readsw(const volatile void __iomem *addr, void *data, int len)
  91. {
  92. void __iomem *a = __isamem_convert_addr(addr);
  93. BUG_ON((unsigned long)addr & 1);
  94. __raw_readsw(a, data, len);
  95. }
  96. EXPORT_SYMBOL(readsw);
  97. void readsl(const volatile void __iomem *addr, void *data, int len)
  98. {
  99. void __iomem *a = __isamem_convert_addr(addr);
  100. BUG_ON((unsigned long)addr & 3);
  101. __raw_readsl(a, data, len);
  102. }
  103. EXPORT_SYMBOL(readsl);
  104. void __writeb(u8 val, volatile void __iomem *addr)
  105. {
  106. void __iomem *a = __isamem_convert_addr(addr);
  107. if ((unsigned long)addr & 1)
  108. __raw_writel(val, a);
  109. else
  110. __raw_writeb(val, a);
  111. }
  112. void __writew(u16 val, volatile void __iomem *addr)
  113. {
  114. void __iomem *a = __isamem_convert_addr(addr);
  115. if ((unsigned long)addr & 1)
  116. BUG();
  117. __raw_writew(val, a);
  118. }
  119. void __writel(u32 val, volatile void __iomem *addr)
  120. {
  121. void __iomem *a = __isamem_convert_addr(addr);
  122. if ((unsigned long)addr & 3)
  123. BUG();
  124. __raw_writew(val, a);
  125. __raw_writew(val >> 16, a + 4);
  126. }
  127. EXPORT_SYMBOL(__writeb);
  128. EXPORT_SYMBOL(__writew);
  129. EXPORT_SYMBOL(__writel);
  130. void writesw(volatile void __iomem *addr, const void *data, int len)
  131. {
  132. void __iomem *a = __isamem_convert_addr(addr);
  133. BUG_ON((unsigned long)addr & 1);
  134. __raw_writesw(a, data, len);
  135. }
  136. EXPORT_SYMBOL(writesw);
  137. void writesl(volatile void __iomem *addr, const void *data, int len)
  138. {
  139. void __iomem *a = __isamem_convert_addr(addr);
  140. BUG_ON((unsigned long)addr & 3);
  141. __raw_writesl(a, data, len);
  142. }
  143. EXPORT_SYMBOL(writesl);
  144. /*
  145. * The EBSA110 has a weird "ISA IO" region:
  146. *
  147. * Region 0 (addr = 0xf0000000 + io << 2)
  148. * --------------------------------------------------------
  149. * Physical region IO region
  150. * f0000fe0 - f0000ffc 3f8 - 3ff ttyS0
  151. * f0000e60 - f0000e64 398 - 399
  152. * f0000de0 - f0000dfc 378 - 37f lp0
  153. * f0000be0 - f0000bfc 2f8 - 2ff ttyS1
  154. *
  155. * Region 1 (addr = 0xf0000000 + (io & ~1) << 1 + (io & 1))
  156. * --------------------------------------------------------
  157. * Physical region IO region
  158. * f00014f1 a79 pnp write data
  159. * f00007c0 - f00007c1 3e0 - 3e1 pcmcia
  160. * f00004f1 279 pnp address
  161. * f0000440 - f000046c 220 - 236 eth0
  162. * f0000405 203 pnp read data
  163. */
  164. #define SUPERIO_PORT(p) \
  165. (((p) >> 3) == (0x3f8 >> 3) || \
  166. ((p) >> 3) == (0x2f8 >> 3) || \
  167. ((p) >> 3) == (0x378 >> 3))
  168. /*
  169. * We're addressing an 8 or 16-bit peripheral which tranfers
  170. * odd addresses on the low ISA byte lane.
  171. */
  172. u8 __inb8(unsigned int port)
  173. {
  174. u32 ret;
  175. /*
  176. * The SuperIO registers use sane addressing techniques...
  177. */
  178. if (SUPERIO_PORT(port))
  179. ret = __raw_readb((void __iomem *)ISAIO_BASE + (port << 2));
  180. else {
  181. void __iomem *a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1);
  182. /*
  183. * Shame nothing else does
  184. */
  185. if (port & 1)
  186. ret = __raw_readl(a);
  187. else
  188. ret = __raw_readb(a);
  189. }
  190. return ret;
  191. }
  192. /*
  193. * We're addressing a 16-bit peripheral which transfers odd
  194. * addresses on the high ISA byte lane.
  195. */
  196. u8 __inb16(unsigned int port)
  197. {
  198. unsigned int offset;
  199. /*
  200. * The SuperIO registers use sane addressing techniques...
  201. */
  202. if (SUPERIO_PORT(port))
  203. offset = port << 2;
  204. else
  205. offset = (port & ~1) << 1 | (port & 1);
  206. return __raw_readb((void __iomem *)ISAIO_BASE + offset);
  207. }
  208. u16 __inw(unsigned int port)
  209. {
  210. unsigned int offset;
  211. /*
  212. * The SuperIO registers use sane addressing techniques...
  213. */
  214. if (SUPERIO_PORT(port))
  215. offset = port << 2;
  216. else {
  217. offset = port << 1;
  218. BUG_ON(port & 1);
  219. }
  220. return __raw_readw((void __iomem *)ISAIO_BASE + offset);
  221. }
  222. /*
  223. * Fake a 32-bit read with two 16-bit reads. Needed for 3c589.
  224. */
  225. u32 __inl(unsigned int port)
  226. {
  227. void __iomem *a;
  228. if (SUPERIO_PORT(port) || port & 3)
  229. BUG();
  230. a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1);
  231. return __raw_readw(a) | __raw_readw(a + 4) << 16;
  232. }
  233. EXPORT_SYMBOL(__inb8);
  234. EXPORT_SYMBOL(__inb16);
  235. EXPORT_SYMBOL(__inw);
  236. EXPORT_SYMBOL(__inl);
  237. void __outb8(u8 val, unsigned int port)
  238. {
  239. /*
  240. * The SuperIO registers use sane addressing techniques...
  241. */
  242. if (SUPERIO_PORT(port))
  243. __raw_writeb(val, (void __iomem *)ISAIO_BASE + (port << 2));
  244. else {
  245. void __iomem *a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1);
  246. /*
  247. * Shame nothing else does
  248. */
  249. if (port & 1)
  250. __raw_writel(val, a);
  251. else
  252. __raw_writeb(val, a);
  253. }
  254. }
  255. void __outb16(u8 val, unsigned int port)
  256. {
  257. unsigned int offset;
  258. /*
  259. * The SuperIO registers use sane addressing techniques...
  260. */
  261. if (SUPERIO_PORT(port))
  262. offset = port << 2;
  263. else
  264. offset = (port & ~1) << 1 | (port & 1);
  265. __raw_writeb(val, (void __iomem *)ISAIO_BASE + offset);
  266. }
  267. void __outw(u16 val, unsigned int port)
  268. {
  269. unsigned int offset;
  270. /*
  271. * The SuperIO registers use sane addressing techniques...
  272. */
  273. if (SUPERIO_PORT(port))
  274. offset = port << 2;
  275. else {
  276. offset = port << 1;
  277. BUG_ON(port & 1);
  278. }
  279. __raw_writew(val, (void __iomem *)ISAIO_BASE + offset);
  280. }
  281. void __outl(u32 val, unsigned int port)
  282. {
  283. BUG();
  284. }
  285. EXPORT_SYMBOL(__outb8);
  286. EXPORT_SYMBOL(__outb16);
  287. EXPORT_SYMBOL(__outw);
  288. EXPORT_SYMBOL(__outl);
  289. void outsb(unsigned int port, const void *from, int len)
  290. {
  291. u32 off;
  292. if (SUPERIO_PORT(port))
  293. off = port << 2;
  294. else {
  295. off = (port & ~1) << 1;
  296. if (port & 1)
  297. BUG();
  298. }
  299. __raw_writesb((void __iomem *)ISAIO_BASE + off, from, len);
  300. }
  301. void insb(unsigned int port, void *from, int len)
  302. {
  303. u32 off;
  304. if (SUPERIO_PORT(port))
  305. off = port << 2;
  306. else {
  307. off = (port & ~1) << 1;
  308. if (port & 1)
  309. BUG();
  310. }
  311. __raw_readsb((void __iomem *)ISAIO_BASE + off, from, len);
  312. }
  313. EXPORT_SYMBOL(outsb);
  314. EXPORT_SYMBOL(insb);
  315. void outsw(unsigned int port, const void *from, int len)
  316. {
  317. u32 off;
  318. if (SUPERIO_PORT(port))
  319. off = port << 2;
  320. else {
  321. off = (port & ~1) << 1;
  322. if (port & 1)
  323. BUG();
  324. }
  325. __raw_writesw((void __iomem *)ISAIO_BASE + off, from, len);
  326. }
  327. void insw(unsigned int port, void *from, int len)
  328. {
  329. u32 off;
  330. if (SUPERIO_PORT(port))
  331. off = port << 2;
  332. else {
  333. off = (port & ~1) << 1;
  334. if (port & 1)
  335. BUG();
  336. }
  337. __raw_readsw((void __iomem *)ISAIO_BASE + off, from, len);
  338. }
  339. EXPORT_SYMBOL(outsw);
  340. EXPORT_SYMBOL(insw);
  341. /*
  342. * We implement these as 16-bit insw/outsw, mainly for
  343. * 3c589 cards.
  344. */
  345. void outsl(unsigned int port, const void *from, int len)
  346. {
  347. u32 off = port << 1;
  348. if (SUPERIO_PORT(port) || port & 3)
  349. BUG();
  350. __raw_writesw((void __iomem *)ISAIO_BASE + off, from, len << 1);
  351. }
  352. void insl(unsigned int port, void *from, int len)
  353. {
  354. u32 off = port << 1;
  355. if (SUPERIO_PORT(port) || port & 3)
  356. BUG();
  357. __raw_readsw((void __iomem *)ISAIO_BASE + off, from, len << 1);
  358. }
  359. EXPORT_SYMBOL(outsl);
  360. EXPORT_SYMBOL(insl);