pm.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * DaVinci Power Management Routines
  4. *
  5. * Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/
  6. */
  7. #include <linux/pm.h>
  8. #include <linux/suspend.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/clk.h>
  12. #include <linux/spinlock.h>
  13. #include <asm/cacheflush.h>
  14. #include <asm/delay.h>
  15. #include <asm/io.h>
  16. #include <mach/common.h>
  17. #include <mach/da8xx.h>
  18. #include <mach/mux.h>
  19. #include <mach/pm.h>
  20. #include "clock.h"
  21. #include "psc.h"
  22. #include "sram.h"
  23. #define DA850_PLL1_BASE 0x01e1a000
  24. #define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF
  25. #define DEEPSLEEP_SLEEPCOUNT 128
  26. static void (*davinci_sram_suspend) (struct davinci_pm_config *);
  27. static struct davinci_pm_config pm_config = {
  28. .sleepcount = DEEPSLEEP_SLEEPCOUNT,
  29. .ddrpsc_num = DA8XX_LPSC1_EMIF3C,
  30. };
  31. static void davinci_sram_push(void *dest, void *src, unsigned int size)
  32. {
  33. memcpy(dest, src, size);
  34. flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
  35. }
  36. static void davinci_pm_suspend(void)
  37. {
  38. unsigned val;
  39. if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
  40. /* Switch CPU PLL to bypass mode */
  41. val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
  42. val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
  43. __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
  44. udelay(PLL_BYPASS_TIME);
  45. /* Powerdown CPU PLL */
  46. val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
  47. val |= PLLCTL_PLLPWRDN;
  48. __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
  49. }
  50. /* Configure sleep count in deep sleep register */
  51. val = __raw_readl(pm_config.deepsleep_reg);
  52. val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
  53. val |= pm_config.sleepcount;
  54. __raw_writel(val, pm_config.deepsleep_reg);
  55. /* System goes to sleep in this call */
  56. davinci_sram_suspend(&pm_config);
  57. if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
  58. /* put CPU PLL in reset */
  59. val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
  60. val &= ~PLLCTL_PLLRST;
  61. __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
  62. /* put CPU PLL in power down */
  63. val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
  64. val &= ~PLLCTL_PLLPWRDN;
  65. __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
  66. /* wait for CPU PLL reset */
  67. udelay(PLL_RESET_TIME);
  68. /* bring CPU PLL out of reset */
  69. val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
  70. val |= PLLCTL_PLLRST;
  71. __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
  72. /* Wait for CPU PLL to lock */
  73. udelay(PLL_LOCK_TIME);
  74. /* Remove CPU PLL from bypass mode */
  75. val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
  76. val &= ~PLLCTL_PLLENSRC;
  77. val |= PLLCTL_PLLEN;
  78. __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
  79. }
  80. }
  81. static int davinci_pm_enter(suspend_state_t state)
  82. {
  83. int ret = 0;
  84. switch (state) {
  85. case PM_SUSPEND_MEM:
  86. davinci_pm_suspend();
  87. break;
  88. default:
  89. ret = -EINVAL;
  90. }
  91. return ret;
  92. }
  93. static const struct platform_suspend_ops davinci_pm_ops = {
  94. .enter = davinci_pm_enter,
  95. .valid = suspend_valid_only_mem,
  96. };
  97. int __init davinci_pm_init(void)
  98. {
  99. int ret;
  100. ret = davinci_cfg_reg(DA850_RTC_ALARM);
  101. if (ret)
  102. return ret;
  103. pm_config.ddr2_ctlr_base = da8xx_get_mem_ctlr();
  104. pm_config.deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
  105. pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
  106. if (!pm_config.cpupll_reg_base)
  107. return -ENOMEM;
  108. pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
  109. if (!pm_config.ddrpll_reg_base) {
  110. ret = -ENOMEM;
  111. goto no_ddrpll_mem;
  112. }
  113. pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
  114. if (!pm_config.ddrpsc_reg_base) {
  115. ret = -ENOMEM;
  116. goto no_ddrpsc_mem;
  117. }
  118. davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
  119. if (!davinci_sram_suspend) {
  120. pr_err("PM: cannot allocate SRAM memory\n");
  121. ret = -ENOMEM;
  122. goto no_sram_mem;
  123. }
  124. davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
  125. davinci_cpu_suspend_sz);
  126. suspend_set_ops(&davinci_pm_ops);
  127. return 0;
  128. no_sram_mem:
  129. iounmap(pm_config.ddrpsc_reg_base);
  130. no_ddrpsc_mem:
  131. iounmap(pm_config.ddrpll_reg_base);
  132. no_ddrpll_mem:
  133. iounmap(pm_config.cpupll_reg_base);
  134. return ret;
  135. }