dm646x.c 18 KB

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  1. /*
  2. * TI DaVinci DM646x chip specific setup
  3. *
  4. * Author: Kevin Hilman, Deep Root Systems, LLC
  5. *
  6. * 2007 (c) Deep Root Systems, LLC. This file is licensed under
  7. * the terms of the GNU General Public License version 2. This program
  8. * is licensed "as is" without any warranty of any kind, whether express
  9. * or implied.
  10. */
  11. #include <linux/clk-provider.h>
  12. #include <linux/clk/davinci.h>
  13. #include <linux/clkdev.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/dmaengine.h>
  16. #include <linux/init.h>
  17. #include <linux/io.h>
  18. #include <linux/irqchip/irq-davinci-aintc.h>
  19. #include <linux/platform_data/edma.h>
  20. #include <linux/platform_data/gpio-davinci.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/serial_8250.h>
  23. #include <asm/mach/map.h>
  24. #include <mach/common.h>
  25. #include <mach/cputype.h>
  26. #include <mach/mux.h>
  27. #include <mach/serial.h>
  28. #include <clocksource/timer-davinci.h>
  29. #include "asp.h"
  30. #include "davinci.h"
  31. #include "irqs.h"
  32. #include "mux.h"
  33. #define DAVINCI_VPIF_BASE (0x01C12000)
  34. #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
  35. BIT_MASK(0))
  36. #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
  37. BIT_MASK(8))
  38. #define DM646X_EMAC_BASE 0x01c80000
  39. #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
  40. #define DM646X_EMAC_CNTRL_OFFSET 0x0000
  41. #define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
  42. #define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
  43. #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
  44. static struct emac_platform_data dm646x_emac_pdata = {
  45. .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
  46. .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
  47. .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
  48. .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
  49. .version = EMAC_VERSION_2,
  50. };
  51. static struct resource dm646x_emac_resources[] = {
  52. {
  53. .start = DM646X_EMAC_BASE,
  54. .end = DM646X_EMAC_BASE + SZ_16K - 1,
  55. .flags = IORESOURCE_MEM,
  56. },
  57. {
  58. .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
  59. .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
  60. .flags = IORESOURCE_IRQ,
  61. },
  62. {
  63. .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
  64. .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
  65. .flags = IORESOURCE_IRQ,
  66. },
  67. {
  68. .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
  69. .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
  70. .flags = IORESOURCE_IRQ,
  71. },
  72. {
  73. .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
  74. .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
  75. .flags = IORESOURCE_IRQ,
  76. },
  77. };
  78. static struct platform_device dm646x_emac_device = {
  79. .name = "davinci_emac",
  80. .id = 1,
  81. .dev = {
  82. .platform_data = &dm646x_emac_pdata,
  83. },
  84. .num_resources = ARRAY_SIZE(dm646x_emac_resources),
  85. .resource = dm646x_emac_resources,
  86. };
  87. static struct resource dm646x_mdio_resources[] = {
  88. {
  89. .start = DM646X_EMAC_MDIO_BASE,
  90. .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
  91. .flags = IORESOURCE_MEM,
  92. },
  93. };
  94. static struct platform_device dm646x_mdio_device = {
  95. .name = "davinci_mdio",
  96. .id = 0,
  97. .num_resources = ARRAY_SIZE(dm646x_mdio_resources),
  98. .resource = dm646x_mdio_resources,
  99. };
  100. /*
  101. * Device specific mux setup
  102. *
  103. * soc description mux mode mode mux dbg
  104. * reg offset mask mode
  105. */
  106. static const struct mux_config dm646x_pins[] = {
  107. #ifdef CONFIG_DAVINCI_MUX
  108. MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
  109. MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
  110. MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
  111. MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
  112. MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
  113. MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
  114. MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
  115. MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
  116. MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
  117. MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
  118. MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
  119. MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
  120. MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
  121. MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
  122. #endif
  123. };
  124. static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
  125. [IRQ_DM646X_VP_VERTINT0] = 7,
  126. [IRQ_DM646X_VP_VERTINT1] = 7,
  127. [IRQ_DM646X_VP_VERTINT2] = 7,
  128. [IRQ_DM646X_VP_VERTINT3] = 7,
  129. [IRQ_DM646X_VP_ERRINT] = 7,
  130. [IRQ_DM646X_RESERVED_1] = 7,
  131. [IRQ_DM646X_RESERVED_2] = 7,
  132. [IRQ_DM646X_WDINT] = 7,
  133. [IRQ_DM646X_CRGENINT0] = 7,
  134. [IRQ_DM646X_CRGENINT1] = 7,
  135. [IRQ_DM646X_TSIFINT0] = 7,
  136. [IRQ_DM646X_TSIFINT1] = 7,
  137. [IRQ_DM646X_VDCEINT] = 7,
  138. [IRQ_DM646X_USBINT] = 7,
  139. [IRQ_DM646X_USBDMAINT] = 7,
  140. [IRQ_DM646X_PCIINT] = 7,
  141. [IRQ_CCINT0] = 7, /* dma */
  142. [IRQ_CCERRINT] = 7, /* dma */
  143. [IRQ_TCERRINT0] = 7, /* dma */
  144. [IRQ_TCERRINT] = 7, /* dma */
  145. [IRQ_DM646X_TCERRINT2] = 7,
  146. [IRQ_DM646X_TCERRINT3] = 7,
  147. [IRQ_DM646X_IDE] = 7,
  148. [IRQ_DM646X_HPIINT] = 7,
  149. [IRQ_DM646X_EMACRXTHINT] = 7,
  150. [IRQ_DM646X_EMACRXINT] = 7,
  151. [IRQ_DM646X_EMACTXINT] = 7,
  152. [IRQ_DM646X_EMACMISCINT] = 7,
  153. [IRQ_DM646X_MCASP0TXINT] = 7,
  154. [IRQ_DM646X_MCASP0RXINT] = 7,
  155. [IRQ_DM646X_RESERVED_3] = 7,
  156. [IRQ_DM646X_MCASP1TXINT] = 7,
  157. [IRQ_TINT0_TINT12] = 7, /* clockevent */
  158. [IRQ_TINT0_TINT34] = 7, /* clocksource */
  159. [IRQ_TINT1_TINT12] = 7, /* DSP timer */
  160. [IRQ_TINT1_TINT34] = 7, /* system tick */
  161. [IRQ_PWMINT0] = 7,
  162. [IRQ_PWMINT1] = 7,
  163. [IRQ_DM646X_VLQINT] = 7,
  164. [IRQ_I2C] = 7,
  165. [IRQ_UARTINT0] = 7,
  166. [IRQ_UARTINT1] = 7,
  167. [IRQ_DM646X_UARTINT2] = 7,
  168. [IRQ_DM646X_SPINT0] = 7,
  169. [IRQ_DM646X_SPINT1] = 7,
  170. [IRQ_DM646X_DSP2ARMINT] = 7,
  171. [IRQ_DM646X_RESERVED_4] = 7,
  172. [IRQ_DM646X_PSCINT] = 7,
  173. [IRQ_DM646X_GPIO0] = 7,
  174. [IRQ_DM646X_GPIO1] = 7,
  175. [IRQ_DM646X_GPIO2] = 7,
  176. [IRQ_DM646X_GPIO3] = 7,
  177. [IRQ_DM646X_GPIO4] = 7,
  178. [IRQ_DM646X_GPIO5] = 7,
  179. [IRQ_DM646X_GPIO6] = 7,
  180. [IRQ_DM646X_GPIO7] = 7,
  181. [IRQ_DM646X_GPIOBNK0] = 7,
  182. [IRQ_DM646X_GPIOBNK1] = 7,
  183. [IRQ_DM646X_GPIOBNK2] = 7,
  184. [IRQ_DM646X_DDRINT] = 7,
  185. [IRQ_DM646X_AEMIFINT] = 7,
  186. [IRQ_COMMTX] = 7,
  187. [IRQ_COMMRX] = 7,
  188. [IRQ_EMUINT] = 7,
  189. };
  190. /*----------------------------------------------------------------------*/
  191. /* Four Transfer Controllers on DM646x */
  192. static s8 dm646x_queue_priority_mapping[][2] = {
  193. /* {event queue no, Priority} */
  194. {0, 4},
  195. {1, 0},
  196. {2, 5},
  197. {3, 1},
  198. {-1, -1},
  199. };
  200. static const struct dma_slave_map dm646x_edma_map[] = {
  201. { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
  202. { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
  203. { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
  204. { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
  205. { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
  206. };
  207. static struct edma_soc_info dm646x_edma_pdata = {
  208. .queue_priority_mapping = dm646x_queue_priority_mapping,
  209. .default_queue = EVENTQ_1,
  210. .slave_map = dm646x_edma_map,
  211. .slavecnt = ARRAY_SIZE(dm646x_edma_map),
  212. };
  213. static struct resource edma_resources[] = {
  214. {
  215. .name = "edma3_cc",
  216. .start = 0x01c00000,
  217. .end = 0x01c00000 + SZ_64K - 1,
  218. .flags = IORESOURCE_MEM,
  219. },
  220. {
  221. .name = "edma3_tc0",
  222. .start = 0x01c10000,
  223. .end = 0x01c10000 + SZ_1K - 1,
  224. .flags = IORESOURCE_MEM,
  225. },
  226. {
  227. .name = "edma3_tc1",
  228. .start = 0x01c10400,
  229. .end = 0x01c10400 + SZ_1K - 1,
  230. .flags = IORESOURCE_MEM,
  231. },
  232. {
  233. .name = "edma3_tc2",
  234. .start = 0x01c10800,
  235. .end = 0x01c10800 + SZ_1K - 1,
  236. .flags = IORESOURCE_MEM,
  237. },
  238. {
  239. .name = "edma3_tc3",
  240. .start = 0x01c10c00,
  241. .end = 0x01c10c00 + SZ_1K - 1,
  242. .flags = IORESOURCE_MEM,
  243. },
  244. {
  245. .name = "edma3_ccint",
  246. .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
  247. .flags = IORESOURCE_IRQ,
  248. },
  249. {
  250. .name = "edma3_ccerrint",
  251. .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
  252. .flags = IORESOURCE_IRQ,
  253. },
  254. /* not using TC*_ERR */
  255. };
  256. static const struct platform_device_info dm646x_edma_device __initconst = {
  257. .name = "edma",
  258. .id = 0,
  259. .dma_mask = DMA_BIT_MASK(32),
  260. .res = edma_resources,
  261. .num_res = ARRAY_SIZE(edma_resources),
  262. .data = &dm646x_edma_pdata,
  263. .size_data = sizeof(dm646x_edma_pdata),
  264. };
  265. static struct resource dm646x_mcasp0_resources[] = {
  266. {
  267. .name = "mpu",
  268. .start = DAVINCI_DM646X_MCASP0_REG_BASE,
  269. .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
  270. .flags = IORESOURCE_MEM,
  271. },
  272. {
  273. .name = "tx",
  274. .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
  275. .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
  276. .flags = IORESOURCE_DMA,
  277. },
  278. {
  279. .name = "rx",
  280. .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
  281. .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
  282. .flags = IORESOURCE_DMA,
  283. },
  284. {
  285. .name = "tx",
  286. .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0TXINT),
  287. .flags = IORESOURCE_IRQ,
  288. },
  289. {
  290. .name = "rx",
  291. .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0RXINT),
  292. .flags = IORESOURCE_IRQ,
  293. },
  294. };
  295. /* DIT mode only, rx is not supported */
  296. static struct resource dm646x_mcasp1_resources[] = {
  297. {
  298. .name = "mpu",
  299. .start = DAVINCI_DM646X_MCASP1_REG_BASE,
  300. .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
  301. .flags = IORESOURCE_MEM,
  302. },
  303. {
  304. .name = "tx",
  305. .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
  306. .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
  307. .flags = IORESOURCE_DMA,
  308. },
  309. {
  310. .name = "tx",
  311. .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP1TXINT),
  312. .flags = IORESOURCE_IRQ,
  313. },
  314. };
  315. static struct platform_device dm646x_mcasp0_device = {
  316. .name = "davinci-mcasp",
  317. .id = 0,
  318. .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
  319. .resource = dm646x_mcasp0_resources,
  320. };
  321. static struct platform_device dm646x_mcasp1_device = {
  322. .name = "davinci-mcasp",
  323. .id = 1,
  324. .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
  325. .resource = dm646x_mcasp1_resources,
  326. };
  327. static struct platform_device dm646x_dit_device = {
  328. .name = "spdif-dit",
  329. .id = -1,
  330. };
  331. static u64 vpif_dma_mask = DMA_BIT_MASK(32);
  332. static struct resource vpif_resource[] = {
  333. {
  334. .start = DAVINCI_VPIF_BASE,
  335. .end = DAVINCI_VPIF_BASE + 0x03ff,
  336. .flags = IORESOURCE_MEM,
  337. }
  338. };
  339. static struct platform_device vpif_dev = {
  340. .name = "vpif",
  341. .id = -1,
  342. .dev = {
  343. .dma_mask = &vpif_dma_mask,
  344. .coherent_dma_mask = DMA_BIT_MASK(32),
  345. },
  346. .resource = vpif_resource,
  347. .num_resources = ARRAY_SIZE(vpif_resource),
  348. };
  349. static struct resource vpif_display_resource[] = {
  350. {
  351. .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
  352. .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
  353. .flags = IORESOURCE_IRQ,
  354. },
  355. {
  356. .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
  357. .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
  358. .flags = IORESOURCE_IRQ,
  359. },
  360. };
  361. static struct platform_device vpif_display_dev = {
  362. .name = "vpif_display",
  363. .id = -1,
  364. .dev = {
  365. .dma_mask = &vpif_dma_mask,
  366. .coherent_dma_mask = DMA_BIT_MASK(32),
  367. },
  368. .resource = vpif_display_resource,
  369. .num_resources = ARRAY_SIZE(vpif_display_resource),
  370. };
  371. static struct resource vpif_capture_resource[] = {
  372. {
  373. .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
  374. .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
  375. .flags = IORESOURCE_IRQ,
  376. },
  377. {
  378. .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
  379. .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
  380. .flags = IORESOURCE_IRQ,
  381. },
  382. };
  383. static struct platform_device vpif_capture_dev = {
  384. .name = "vpif_capture",
  385. .id = -1,
  386. .dev = {
  387. .dma_mask = &vpif_dma_mask,
  388. .coherent_dma_mask = DMA_BIT_MASK(32),
  389. },
  390. .resource = vpif_capture_resource,
  391. .num_resources = ARRAY_SIZE(vpif_capture_resource),
  392. };
  393. static struct resource dm646x_gpio_resources[] = {
  394. { /* registers */
  395. .start = DAVINCI_GPIO_BASE,
  396. .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
  397. .flags = IORESOURCE_MEM,
  398. },
  399. { /* interrupt */
  400. .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
  401. .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
  402. .flags = IORESOURCE_IRQ,
  403. },
  404. {
  405. .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
  406. .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
  407. .flags = IORESOURCE_IRQ,
  408. },
  409. {
  410. .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
  411. .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
  412. .flags = IORESOURCE_IRQ,
  413. },
  414. };
  415. static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
  416. .no_auto_base = true,
  417. .base = 0,
  418. .ngpio = 43,
  419. };
  420. int __init dm646x_gpio_register(void)
  421. {
  422. return davinci_gpio_register(dm646x_gpio_resources,
  423. ARRAY_SIZE(dm646x_gpio_resources),
  424. &dm646x_gpio_platform_data);
  425. }
  426. /*----------------------------------------------------------------------*/
  427. static struct map_desc dm646x_io_desc[] = {
  428. {
  429. .virtual = IO_VIRT,
  430. .pfn = __phys_to_pfn(IO_PHYS),
  431. .length = IO_SIZE,
  432. .type = MT_DEVICE
  433. },
  434. };
  435. /* Contents of JTAG ID register used to identify exact cpu type */
  436. static struct davinci_id dm646x_ids[] = {
  437. {
  438. .variant = 0x0,
  439. .part_no = 0xb770,
  440. .manufacturer = 0x017,
  441. .cpu_id = DAVINCI_CPU_ID_DM6467,
  442. .name = "dm6467_rev1.x",
  443. },
  444. {
  445. .variant = 0x1,
  446. .part_no = 0xb770,
  447. .manufacturer = 0x017,
  448. .cpu_id = DAVINCI_CPU_ID_DM6467,
  449. .name = "dm6467_rev3.x",
  450. },
  451. };
  452. /*
  453. * Bottom half of timer0 is used for clockevent, top half is used for
  454. * clocksource.
  455. */
  456. static const struct davinci_timer_cfg dm646x_timer_cfg = {
  457. .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
  458. .irq = {
  459. DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
  460. DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
  461. },
  462. };
  463. static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
  464. {
  465. .mapbase = DAVINCI_UART0_BASE,
  466. .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
  467. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  468. UPF_IOREMAP,
  469. .iotype = UPIO_MEM32,
  470. .regshift = 2,
  471. },
  472. {
  473. .flags = 0,
  474. }
  475. };
  476. static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
  477. {
  478. .mapbase = DAVINCI_UART1_BASE,
  479. .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
  480. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  481. UPF_IOREMAP,
  482. .iotype = UPIO_MEM32,
  483. .regshift = 2,
  484. },
  485. {
  486. .flags = 0,
  487. }
  488. };
  489. static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
  490. {
  491. .mapbase = DAVINCI_UART2_BASE,
  492. .irq = DAVINCI_INTC_IRQ(IRQ_DM646X_UARTINT2),
  493. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  494. UPF_IOREMAP,
  495. .iotype = UPIO_MEM32,
  496. .regshift = 2,
  497. },
  498. {
  499. .flags = 0,
  500. }
  501. };
  502. struct platform_device dm646x_serial_device[] = {
  503. {
  504. .name = "serial8250",
  505. .id = PLAT8250_DEV_PLATFORM,
  506. .dev = {
  507. .platform_data = dm646x_serial0_platform_data,
  508. }
  509. },
  510. {
  511. .name = "serial8250",
  512. .id = PLAT8250_DEV_PLATFORM1,
  513. .dev = {
  514. .platform_data = dm646x_serial1_platform_data,
  515. }
  516. },
  517. {
  518. .name = "serial8250",
  519. .id = PLAT8250_DEV_PLATFORM2,
  520. .dev = {
  521. .platform_data = dm646x_serial2_platform_data,
  522. }
  523. },
  524. {
  525. }
  526. };
  527. static const struct davinci_soc_info davinci_soc_info_dm646x = {
  528. .io_desc = dm646x_io_desc,
  529. .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
  530. .jtag_id_reg = 0x01c40028,
  531. .ids = dm646x_ids,
  532. .ids_num = ARRAY_SIZE(dm646x_ids),
  533. .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
  534. .pinmux_pins = dm646x_pins,
  535. .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
  536. .emac_pdata = &dm646x_emac_pdata,
  537. .sram_dma = 0x10010000,
  538. .sram_len = SZ_32K,
  539. };
  540. void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
  541. {
  542. dm646x_mcasp0_device.dev.platform_data = pdata;
  543. platform_device_register(&dm646x_mcasp0_device);
  544. }
  545. void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
  546. {
  547. dm646x_mcasp1_device.dev.platform_data = pdata;
  548. platform_device_register(&dm646x_mcasp1_device);
  549. platform_device_register(&dm646x_dit_device);
  550. }
  551. void dm646x_setup_vpif(struct vpif_display_config *display_config,
  552. struct vpif_capture_config *capture_config)
  553. {
  554. unsigned int value;
  555. value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
  556. value &= ~VSCLKDIS_MASK;
  557. __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
  558. value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
  559. value &= ~VDD3P3V_VID_MASK;
  560. __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
  561. davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
  562. davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
  563. davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
  564. davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
  565. vpif_display_dev.dev.platform_data = display_config;
  566. vpif_capture_dev.dev.platform_data = capture_config;
  567. platform_device_register(&vpif_dev);
  568. platform_device_register(&vpif_display_dev);
  569. platform_device_register(&vpif_capture_dev);
  570. }
  571. int __init dm646x_init_edma(struct edma_rsv_info *rsv)
  572. {
  573. struct platform_device *edma_pdev;
  574. dm646x_edma_pdata.rsv = rsv;
  575. edma_pdev = platform_device_register_full(&dm646x_edma_device);
  576. return PTR_ERR_OR_ZERO(edma_pdev);
  577. }
  578. void __init dm646x_init(void)
  579. {
  580. davinci_common_init(&davinci_soc_info_dm646x);
  581. davinci_map_sysmod();
  582. }
  583. void __init dm646x_init_time(unsigned long ref_clk_rate,
  584. unsigned long aux_clkin_rate)
  585. {
  586. void __iomem *pll1, *psc;
  587. struct clk *clk;
  588. int rv;
  589. clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate);
  590. clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate);
  591. pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
  592. dm646x_pll1_init(NULL, pll1, NULL);
  593. psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
  594. dm646x_psc_init(NULL, psc);
  595. clk = clk_get(NULL, "timer0");
  596. if (WARN_ON(IS_ERR(clk))) {
  597. pr_err("Unable to get the timer clock\n");
  598. return;
  599. }
  600. rv = davinci_timer_register(clk, &dm646x_timer_cfg);
  601. WARN(rv, "Unable to register the timer: %d\n", rv);
  602. }
  603. static struct resource dm646x_pll2_resources[] = {
  604. {
  605. .start = DAVINCI_PLL2_BASE,
  606. .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
  607. .flags = IORESOURCE_MEM,
  608. },
  609. };
  610. static struct platform_device dm646x_pll2_device = {
  611. .name = "dm646x-pll2",
  612. .id = -1,
  613. .resource = dm646x_pll2_resources,
  614. .num_resources = ARRAY_SIZE(dm646x_pll2_resources),
  615. };
  616. void __init dm646x_register_clocks(void)
  617. {
  618. /* PLL1 and PSC are registered in dm646x_init_time() */
  619. platform_device_register(&dm646x_pll2_device);
  620. }
  621. static const struct davinci_aintc_config dm646x_aintc_config = {
  622. .reg = {
  623. .start = DAVINCI_ARM_INTC_BASE,
  624. .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
  625. .flags = IORESOURCE_MEM,
  626. },
  627. .num_irqs = 64,
  628. .prios = dm646x_default_priorities,
  629. };
  630. void __init dm646x_init_irq(void)
  631. {
  632. davinci_aintc_init(&dm646x_aintc_config);
  633. }
  634. static int __init dm646x_init_devices(void)
  635. {
  636. int ret = 0;
  637. if (!cpu_is_davinci_dm646x())
  638. return 0;
  639. platform_device_register(&dm646x_mdio_device);
  640. platform_device_register(&dm646x_emac_device);
  641. ret = davinci_init_wdt();
  642. if (ret)
  643. pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
  644. return ret;
  645. }
  646. postcore_initcall(dm646x_init_devices);