dm365.c 30 KB

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  1. /*
  2. * TI DaVinci DM365 chip specific setup
  3. *
  4. * Copyright (C) 2009 Texas Instruments
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/clk-provider.h>
  16. #include <linux/clk/davinci.h>
  17. #include <linux/clkdev.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/dmaengine.h>
  20. #include <linux/init.h>
  21. #include <linux/io.h>
  22. #include <linux/irqchip/irq-davinci-aintc.h>
  23. #include <linux/platform_data/edma.h>
  24. #include <linux/platform_data/gpio-davinci.h>
  25. #include <linux/platform_data/keyscan-davinci.h>
  26. #include <linux/platform_data/spi-davinci.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/serial_8250.h>
  29. #include <linux/spi/spi.h>
  30. #include <asm/mach/map.h>
  31. #include <mach/common.h>
  32. #include <mach/cputype.h>
  33. #include <mach/mux.h>
  34. #include <mach/serial.h>
  35. #include <clocksource/timer-davinci.h>
  36. #include "asp.h"
  37. #include "davinci.h"
  38. #include "irqs.h"
  39. #include "mux.h"
  40. #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
  41. #define DM365_RTC_BASE 0x01c69000
  42. #define DM365_KEYSCAN_BASE 0x01c69400
  43. #define DM365_OSD_BASE 0x01c71c00
  44. #define DM365_VENC_BASE 0x01c71e00
  45. #define DAVINCI_DM365_VC_BASE 0x01d0c000
  46. #define DAVINCI_DMA_VC_TX 2
  47. #define DAVINCI_DMA_VC_RX 3
  48. #define DM365_EMAC_BASE 0x01d07000
  49. #define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
  50. #define DM365_EMAC_CNTRL_OFFSET 0x0000
  51. #define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
  52. #define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
  53. #define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
  54. #define INTMUX 0x18
  55. #define EVTMUX 0x1c
  56. static const struct mux_config dm365_pins[] = {
  57. #ifdef CONFIG_DAVINCI_MUX
  58. MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
  59. MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
  60. MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
  61. MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
  62. MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
  63. MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
  64. MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
  65. MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
  66. MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
  67. MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
  68. MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
  69. MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
  70. MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
  71. MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
  72. MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
  73. MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
  74. MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
  75. MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
  76. MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
  77. MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
  78. MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
  79. MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
  80. MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
  81. MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
  82. MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
  83. MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
  84. MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
  85. MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
  86. MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
  87. MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
  88. MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
  89. MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
  90. MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
  91. MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
  92. MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
  93. MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
  94. MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
  95. MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
  96. MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
  97. MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
  98. MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
  99. MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
  100. MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
  101. MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
  102. MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
  103. MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
  104. MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
  105. MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
  106. MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
  107. MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
  108. MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
  109. MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
  110. MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
  111. MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
  112. MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
  113. MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
  114. MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
  115. MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
  116. MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
  117. MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
  118. MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
  119. MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
  120. MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
  121. MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
  122. MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
  123. MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
  124. MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
  125. MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
  126. MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
  127. MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
  128. MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
  129. MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
  130. MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
  131. MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
  132. MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
  133. MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
  134. MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
  135. MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
  136. MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
  137. MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
  138. MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
  139. MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
  140. MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
  141. MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
  142. MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
  143. MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
  144. MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
  145. MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
  146. MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
  147. MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
  148. MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
  149. MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
  150. MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
  151. MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
  152. MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
  153. MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
  154. MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
  155. MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
  156. MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
  157. MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
  158. MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
  159. MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
  160. MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
  161. MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
  162. INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
  163. INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
  164. INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
  165. INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
  166. INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
  167. INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
  168. INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
  169. INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
  170. INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
  171. INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
  172. INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
  173. INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
  174. INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
  175. INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
  176. INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
  177. INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
  178. INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
  179. INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
  180. EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
  181. EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
  182. EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
  183. EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
  184. #endif
  185. };
  186. static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
  187. static struct davinci_spi_platform_data dm365_spi0_pdata = {
  188. .version = SPI_VERSION_1,
  189. .num_chipselect = 2,
  190. .dma_event_q = EVENTQ_3,
  191. .prescaler_limit = 1,
  192. };
  193. static struct resource dm365_spi0_resources[] = {
  194. {
  195. .start = 0x01c66000,
  196. .end = 0x01c667ff,
  197. .flags = IORESOURCE_MEM,
  198. },
  199. {
  200. .start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0),
  201. .flags = IORESOURCE_IRQ,
  202. },
  203. };
  204. static struct platform_device dm365_spi0_device = {
  205. .name = "spi_davinci",
  206. .id = 0,
  207. .dev = {
  208. .dma_mask = &dm365_spi0_dma_mask,
  209. .coherent_dma_mask = DMA_BIT_MASK(32),
  210. .platform_data = &dm365_spi0_pdata,
  211. },
  212. .num_resources = ARRAY_SIZE(dm365_spi0_resources),
  213. .resource = dm365_spi0_resources,
  214. };
  215. void __init dm365_init_spi0(unsigned chipselect_mask,
  216. const struct spi_board_info *info, unsigned len)
  217. {
  218. davinci_cfg_reg(DM365_SPI0_SCLK);
  219. davinci_cfg_reg(DM365_SPI0_SDI);
  220. davinci_cfg_reg(DM365_SPI0_SDO);
  221. /* not all slaves will be wired up */
  222. if (chipselect_mask & BIT(0))
  223. davinci_cfg_reg(DM365_SPI0_SDENA0);
  224. if (chipselect_mask & BIT(1))
  225. davinci_cfg_reg(DM365_SPI0_SDENA1);
  226. spi_register_board_info(info, len);
  227. platform_device_register(&dm365_spi0_device);
  228. }
  229. static struct resource dm365_gpio_resources[] = {
  230. { /* registers */
  231. .start = DAVINCI_GPIO_BASE,
  232. .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
  233. .flags = IORESOURCE_MEM,
  234. },
  235. { /* interrupt */
  236. .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
  237. .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
  238. .flags = IORESOURCE_IRQ,
  239. },
  240. {
  241. .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
  242. .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
  243. .flags = IORESOURCE_IRQ,
  244. },
  245. {
  246. .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
  247. .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
  248. .flags = IORESOURCE_IRQ,
  249. },
  250. {
  251. .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
  252. .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
  253. .flags = IORESOURCE_IRQ,
  254. },
  255. {
  256. .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
  257. .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
  258. .flags = IORESOURCE_IRQ,
  259. },
  260. {
  261. .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
  262. .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
  263. .flags = IORESOURCE_IRQ,
  264. },
  265. {
  266. .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
  267. .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
  268. .flags = IORESOURCE_IRQ,
  269. },
  270. {
  271. .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
  272. .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
  273. .flags = IORESOURCE_IRQ,
  274. },
  275. };
  276. static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
  277. .no_auto_base = true,
  278. .base = 0,
  279. .ngpio = 104,
  280. .gpio_unbanked = 8,
  281. };
  282. int __init dm365_gpio_register(void)
  283. {
  284. return davinci_gpio_register(dm365_gpio_resources,
  285. ARRAY_SIZE(dm365_gpio_resources),
  286. &dm365_gpio_platform_data);
  287. }
  288. static struct emac_platform_data dm365_emac_pdata = {
  289. .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
  290. .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
  291. .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
  292. .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
  293. .version = EMAC_VERSION_2,
  294. };
  295. static struct resource dm365_emac_resources[] = {
  296. {
  297. .start = DM365_EMAC_BASE,
  298. .end = DM365_EMAC_BASE + SZ_16K - 1,
  299. .flags = IORESOURCE_MEM,
  300. },
  301. {
  302. .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
  303. .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
  304. .flags = IORESOURCE_IRQ,
  305. },
  306. {
  307. .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
  308. .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
  309. .flags = IORESOURCE_IRQ,
  310. },
  311. {
  312. .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
  313. .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
  314. .flags = IORESOURCE_IRQ,
  315. },
  316. {
  317. .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
  318. .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
  319. .flags = IORESOURCE_IRQ,
  320. },
  321. };
  322. static struct platform_device dm365_emac_device = {
  323. .name = "davinci_emac",
  324. .id = 1,
  325. .dev = {
  326. .platform_data = &dm365_emac_pdata,
  327. },
  328. .num_resources = ARRAY_SIZE(dm365_emac_resources),
  329. .resource = dm365_emac_resources,
  330. };
  331. static struct resource dm365_mdio_resources[] = {
  332. {
  333. .start = DM365_EMAC_MDIO_BASE,
  334. .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
  335. .flags = IORESOURCE_MEM,
  336. },
  337. };
  338. static struct platform_device dm365_mdio_device = {
  339. .name = "davinci_mdio",
  340. .id = 0,
  341. .num_resources = ARRAY_SIZE(dm365_mdio_resources),
  342. .resource = dm365_mdio_resources,
  343. };
  344. static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
  345. [IRQ_VDINT0] = 2,
  346. [IRQ_VDINT1] = 6,
  347. [IRQ_VDINT2] = 6,
  348. [IRQ_HISTINT] = 6,
  349. [IRQ_H3AINT] = 6,
  350. [IRQ_PRVUINT] = 6,
  351. [IRQ_RSZINT] = 6,
  352. [IRQ_DM365_INSFINT] = 7,
  353. [IRQ_VENCINT] = 6,
  354. [IRQ_ASQINT] = 6,
  355. [IRQ_IMXINT] = 6,
  356. [IRQ_DM365_IMCOPINT] = 4,
  357. [IRQ_USBINT] = 4,
  358. [IRQ_DM365_RTOINT] = 7,
  359. [IRQ_DM365_TINT5] = 7,
  360. [IRQ_DM365_TINT6] = 5,
  361. [IRQ_CCINT0] = 5,
  362. [IRQ_CCERRINT] = 5,
  363. [IRQ_TCERRINT0] = 5,
  364. [IRQ_TCERRINT] = 7,
  365. [IRQ_PSCIN] = 4,
  366. [IRQ_DM365_SPINT2_1] = 7,
  367. [IRQ_DM365_TINT7] = 7,
  368. [IRQ_DM365_SDIOINT0] = 7,
  369. [IRQ_MBXINT] = 7,
  370. [IRQ_MBRINT] = 7,
  371. [IRQ_MMCINT] = 7,
  372. [IRQ_DM365_MMCINT1] = 7,
  373. [IRQ_DM365_PWMINT3] = 7,
  374. [IRQ_AEMIFINT] = 2,
  375. [IRQ_DM365_SDIOINT1] = 2,
  376. [IRQ_TINT0_TINT12] = 7,
  377. [IRQ_TINT0_TINT34] = 7,
  378. [IRQ_TINT1_TINT12] = 7,
  379. [IRQ_TINT1_TINT34] = 7,
  380. [IRQ_PWMINT0] = 7,
  381. [IRQ_PWMINT1] = 3,
  382. [IRQ_PWMINT2] = 3,
  383. [IRQ_I2C] = 3,
  384. [IRQ_UARTINT0] = 3,
  385. [IRQ_UARTINT1] = 3,
  386. [IRQ_DM365_RTCINT] = 3,
  387. [IRQ_DM365_SPIINT0_0] = 3,
  388. [IRQ_DM365_SPIINT3_0] = 3,
  389. [IRQ_DM365_GPIO0] = 3,
  390. [IRQ_DM365_GPIO1] = 7,
  391. [IRQ_DM365_GPIO2] = 4,
  392. [IRQ_DM365_GPIO3] = 4,
  393. [IRQ_DM365_GPIO4] = 7,
  394. [IRQ_DM365_GPIO5] = 7,
  395. [IRQ_DM365_GPIO6] = 7,
  396. [IRQ_DM365_GPIO7] = 7,
  397. [IRQ_DM365_EMAC_RXTHRESH] = 7,
  398. [IRQ_DM365_EMAC_RXPULSE] = 7,
  399. [IRQ_DM365_EMAC_TXPULSE] = 7,
  400. [IRQ_DM365_EMAC_MISCPULSE] = 7,
  401. [IRQ_DM365_GPIO12] = 7,
  402. [IRQ_DM365_GPIO13] = 7,
  403. [IRQ_DM365_GPIO14] = 7,
  404. [IRQ_DM365_GPIO15] = 7,
  405. [IRQ_DM365_KEYINT] = 7,
  406. [IRQ_DM365_TCERRINT2] = 7,
  407. [IRQ_DM365_TCERRINT3] = 7,
  408. [IRQ_DM365_EMUINT] = 7,
  409. };
  410. /* Four Transfer Controllers on DM365 */
  411. static s8 dm365_queue_priority_mapping[][2] = {
  412. /* {event queue no, Priority} */
  413. {0, 7},
  414. {1, 7},
  415. {2, 7},
  416. {3, 0},
  417. {-1, -1},
  418. };
  419. static const struct dma_slave_map dm365_edma_map[] = {
  420. { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
  421. { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
  422. { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
  423. { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
  424. { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
  425. { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
  426. { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
  427. { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
  428. { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
  429. { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
  430. { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
  431. { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
  432. { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
  433. { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
  434. { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
  435. { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
  436. };
  437. static struct edma_soc_info dm365_edma_pdata = {
  438. .queue_priority_mapping = dm365_queue_priority_mapping,
  439. .default_queue = EVENTQ_3,
  440. .slave_map = dm365_edma_map,
  441. .slavecnt = ARRAY_SIZE(dm365_edma_map),
  442. };
  443. static struct resource edma_resources[] = {
  444. {
  445. .name = "edma3_cc",
  446. .start = 0x01c00000,
  447. .end = 0x01c00000 + SZ_64K - 1,
  448. .flags = IORESOURCE_MEM,
  449. },
  450. {
  451. .name = "edma3_tc0",
  452. .start = 0x01c10000,
  453. .end = 0x01c10000 + SZ_1K - 1,
  454. .flags = IORESOURCE_MEM,
  455. },
  456. {
  457. .name = "edma3_tc1",
  458. .start = 0x01c10400,
  459. .end = 0x01c10400 + SZ_1K - 1,
  460. .flags = IORESOURCE_MEM,
  461. },
  462. {
  463. .name = "edma3_tc2",
  464. .start = 0x01c10800,
  465. .end = 0x01c10800 + SZ_1K - 1,
  466. .flags = IORESOURCE_MEM,
  467. },
  468. {
  469. .name = "edma3_tc3",
  470. .start = 0x01c10c00,
  471. .end = 0x01c10c00 + SZ_1K - 1,
  472. .flags = IORESOURCE_MEM,
  473. },
  474. {
  475. .name = "edma3_ccint",
  476. .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
  477. .flags = IORESOURCE_IRQ,
  478. },
  479. {
  480. .name = "edma3_ccerrint",
  481. .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
  482. .flags = IORESOURCE_IRQ,
  483. },
  484. /* not using TC*_ERR */
  485. };
  486. static const struct platform_device_info dm365_edma_device __initconst = {
  487. .name = "edma",
  488. .id = 0,
  489. .dma_mask = DMA_BIT_MASK(32),
  490. .res = edma_resources,
  491. .num_res = ARRAY_SIZE(edma_resources),
  492. .data = &dm365_edma_pdata,
  493. .size_data = sizeof(dm365_edma_pdata),
  494. };
  495. static struct resource dm365_asp_resources[] = {
  496. {
  497. .name = "mpu",
  498. .start = DAVINCI_DM365_ASP0_BASE,
  499. .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
  500. .flags = IORESOURCE_MEM,
  501. },
  502. {
  503. .start = DAVINCI_DMA_ASP0_TX,
  504. .end = DAVINCI_DMA_ASP0_TX,
  505. .flags = IORESOURCE_DMA,
  506. },
  507. {
  508. .start = DAVINCI_DMA_ASP0_RX,
  509. .end = DAVINCI_DMA_ASP0_RX,
  510. .flags = IORESOURCE_DMA,
  511. },
  512. };
  513. static struct platform_device dm365_asp_device = {
  514. .name = "davinci-mcbsp",
  515. .id = -1,
  516. .num_resources = ARRAY_SIZE(dm365_asp_resources),
  517. .resource = dm365_asp_resources,
  518. };
  519. static struct resource dm365_vc_resources[] = {
  520. {
  521. .start = DAVINCI_DM365_VC_BASE,
  522. .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
  523. .flags = IORESOURCE_MEM,
  524. },
  525. {
  526. .start = DAVINCI_DMA_VC_TX,
  527. .end = DAVINCI_DMA_VC_TX,
  528. .flags = IORESOURCE_DMA,
  529. },
  530. {
  531. .start = DAVINCI_DMA_VC_RX,
  532. .end = DAVINCI_DMA_VC_RX,
  533. .flags = IORESOURCE_DMA,
  534. },
  535. };
  536. static struct platform_device dm365_vc_device = {
  537. .name = "davinci_voicecodec",
  538. .id = -1,
  539. .num_resources = ARRAY_SIZE(dm365_vc_resources),
  540. .resource = dm365_vc_resources,
  541. };
  542. static struct resource dm365_rtc_resources[] = {
  543. {
  544. .start = DM365_RTC_BASE,
  545. .end = DM365_RTC_BASE + SZ_1K - 1,
  546. .flags = IORESOURCE_MEM,
  547. },
  548. {
  549. .start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT),
  550. .flags = IORESOURCE_IRQ,
  551. },
  552. };
  553. static struct platform_device dm365_rtc_device = {
  554. .name = "rtc_davinci",
  555. .id = 0,
  556. .num_resources = ARRAY_SIZE(dm365_rtc_resources),
  557. .resource = dm365_rtc_resources,
  558. };
  559. static struct map_desc dm365_io_desc[] = {
  560. {
  561. .virtual = IO_VIRT,
  562. .pfn = __phys_to_pfn(IO_PHYS),
  563. .length = IO_SIZE,
  564. .type = MT_DEVICE
  565. },
  566. };
  567. static struct resource dm365_ks_resources[] = {
  568. {
  569. /* registers */
  570. .start = DM365_KEYSCAN_BASE,
  571. .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
  572. .flags = IORESOURCE_MEM,
  573. },
  574. {
  575. /* interrupt */
  576. .start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
  577. .end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
  578. .flags = IORESOURCE_IRQ,
  579. },
  580. };
  581. static struct platform_device dm365_ks_device = {
  582. .name = "davinci_keyscan",
  583. .id = 0,
  584. .num_resources = ARRAY_SIZE(dm365_ks_resources),
  585. .resource = dm365_ks_resources,
  586. };
  587. /* Contents of JTAG ID register used to identify exact cpu type */
  588. static struct davinci_id dm365_ids[] = {
  589. {
  590. .variant = 0x0,
  591. .part_no = 0xb83e,
  592. .manufacturer = 0x017,
  593. .cpu_id = DAVINCI_CPU_ID_DM365,
  594. .name = "dm365_rev1.1",
  595. },
  596. {
  597. .variant = 0x8,
  598. .part_no = 0xb83e,
  599. .manufacturer = 0x017,
  600. .cpu_id = DAVINCI_CPU_ID_DM365,
  601. .name = "dm365_rev1.2",
  602. },
  603. };
  604. /*
  605. * Bottom half of timer0 is used for clockevent, top half is used for
  606. * clocksource.
  607. */
  608. static const struct davinci_timer_cfg dm365_timer_cfg = {
  609. .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128),
  610. .irq = {
  611. DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
  612. DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
  613. },
  614. };
  615. #define DM365_UART1_BASE (IO_PHYS + 0x106000)
  616. static struct plat_serial8250_port dm365_serial0_platform_data[] = {
  617. {
  618. .mapbase = DAVINCI_UART0_BASE,
  619. .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
  620. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  621. UPF_IOREMAP,
  622. .iotype = UPIO_MEM,
  623. .regshift = 2,
  624. },
  625. {
  626. .flags = 0,
  627. }
  628. };
  629. static struct plat_serial8250_port dm365_serial1_platform_data[] = {
  630. {
  631. .mapbase = DM365_UART1_BASE,
  632. .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
  633. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  634. UPF_IOREMAP,
  635. .iotype = UPIO_MEM,
  636. .regshift = 2,
  637. },
  638. {
  639. .flags = 0,
  640. }
  641. };
  642. struct platform_device dm365_serial_device[] = {
  643. {
  644. .name = "serial8250",
  645. .id = PLAT8250_DEV_PLATFORM,
  646. .dev = {
  647. .platform_data = dm365_serial0_platform_data,
  648. }
  649. },
  650. {
  651. .name = "serial8250",
  652. .id = PLAT8250_DEV_PLATFORM1,
  653. .dev = {
  654. .platform_data = dm365_serial1_platform_data,
  655. }
  656. },
  657. {
  658. }
  659. };
  660. static const struct davinci_soc_info davinci_soc_info_dm365 = {
  661. .io_desc = dm365_io_desc,
  662. .io_desc_num = ARRAY_SIZE(dm365_io_desc),
  663. .jtag_id_reg = 0x01c40028,
  664. .ids = dm365_ids,
  665. .ids_num = ARRAY_SIZE(dm365_ids),
  666. .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
  667. .pinmux_pins = dm365_pins,
  668. .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
  669. .emac_pdata = &dm365_emac_pdata,
  670. .sram_dma = 0x00010000,
  671. .sram_len = SZ_32K,
  672. };
  673. void __init dm365_init_asp(void)
  674. {
  675. davinci_cfg_reg(DM365_MCBSP0_BDX);
  676. davinci_cfg_reg(DM365_MCBSP0_X);
  677. davinci_cfg_reg(DM365_MCBSP0_BFSX);
  678. davinci_cfg_reg(DM365_MCBSP0_BDR);
  679. davinci_cfg_reg(DM365_MCBSP0_R);
  680. davinci_cfg_reg(DM365_MCBSP0_BFSR);
  681. davinci_cfg_reg(DM365_EVT2_ASP_TX);
  682. davinci_cfg_reg(DM365_EVT3_ASP_RX);
  683. platform_device_register(&dm365_asp_device);
  684. }
  685. void __init dm365_init_vc(void)
  686. {
  687. davinci_cfg_reg(DM365_EVT2_VC_TX);
  688. davinci_cfg_reg(DM365_EVT3_VC_RX);
  689. platform_device_register(&dm365_vc_device);
  690. }
  691. void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
  692. {
  693. dm365_ks_device.dev.platform_data = pdata;
  694. platform_device_register(&dm365_ks_device);
  695. }
  696. void __init dm365_init_rtc(void)
  697. {
  698. davinci_cfg_reg(DM365_INT_PRTCSS);
  699. platform_device_register(&dm365_rtc_device);
  700. }
  701. void __init dm365_init(void)
  702. {
  703. davinci_common_init(&davinci_soc_info_dm365);
  704. davinci_map_sysmod();
  705. }
  706. void __init dm365_init_time(void)
  707. {
  708. void __iomem *pll1, *pll2, *psc;
  709. struct clk *clk;
  710. int rv;
  711. clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
  712. pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
  713. dm365_pll1_init(NULL, pll1, NULL);
  714. pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K);
  715. dm365_pll2_init(NULL, pll2, NULL);
  716. psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
  717. dm365_psc_init(NULL, psc);
  718. clk = clk_get(NULL, "timer0");
  719. if (WARN_ON(IS_ERR(clk))) {
  720. pr_err("Unable to get the timer clock\n");
  721. return;
  722. }
  723. rv = davinci_timer_register(clk, &dm365_timer_cfg);
  724. WARN(rv, "Unable to register the timer: %d\n", rv);
  725. }
  726. void __init dm365_register_clocks(void)
  727. {
  728. /* all clocks are currently registered in dm365_init_time() */
  729. }
  730. static struct resource dm365_vpss_resources[] = {
  731. {
  732. /* VPSS ISP5 Base address */
  733. .name = "isp5",
  734. .start = 0x01c70000,
  735. .end = 0x01c70000 + 0xff,
  736. .flags = IORESOURCE_MEM,
  737. },
  738. {
  739. /* VPSS CLK Base address */
  740. .name = "vpss",
  741. .start = 0x01c70200,
  742. .end = 0x01c70200 + 0xff,
  743. .flags = IORESOURCE_MEM,
  744. },
  745. };
  746. static struct platform_device dm365_vpss_device = {
  747. .name = "vpss",
  748. .id = -1,
  749. .dev.platform_data = "dm365_vpss",
  750. .num_resources = ARRAY_SIZE(dm365_vpss_resources),
  751. .resource = dm365_vpss_resources,
  752. };
  753. static struct resource vpfe_resources[] = {
  754. {
  755. .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
  756. .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
  757. .flags = IORESOURCE_IRQ,
  758. },
  759. {
  760. .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
  761. .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
  762. .flags = IORESOURCE_IRQ,
  763. },
  764. };
  765. static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
  766. static struct platform_device vpfe_capture_dev = {
  767. .name = CAPTURE_DRV_NAME,
  768. .id = -1,
  769. .num_resources = ARRAY_SIZE(vpfe_resources),
  770. .resource = vpfe_resources,
  771. .dev = {
  772. .dma_mask = &vpfe_capture_dma_mask,
  773. .coherent_dma_mask = DMA_BIT_MASK(32),
  774. },
  775. };
  776. static void dm365_isif_setup_pinmux(void)
  777. {
  778. davinci_cfg_reg(DM365_VIN_CAM_WEN);
  779. davinci_cfg_reg(DM365_VIN_CAM_VD);
  780. davinci_cfg_reg(DM365_VIN_CAM_HD);
  781. davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
  782. davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
  783. }
  784. static struct resource isif_resource[] = {
  785. /* ISIF Base address */
  786. {
  787. .start = 0x01c71000,
  788. .end = 0x01c71000 + 0x1ff,
  789. .flags = IORESOURCE_MEM,
  790. },
  791. /* ISIF Linearization table 0 */
  792. {
  793. .start = 0x1C7C000,
  794. .end = 0x1C7C000 + 0x2ff,
  795. .flags = IORESOURCE_MEM,
  796. },
  797. /* ISIF Linearization table 1 */
  798. {
  799. .start = 0x1C7C400,
  800. .end = 0x1C7C400 + 0x2ff,
  801. .flags = IORESOURCE_MEM,
  802. },
  803. };
  804. static struct platform_device dm365_isif_dev = {
  805. .name = "isif",
  806. .id = -1,
  807. .num_resources = ARRAY_SIZE(isif_resource),
  808. .resource = isif_resource,
  809. .dev = {
  810. .dma_mask = &vpfe_capture_dma_mask,
  811. .coherent_dma_mask = DMA_BIT_MASK(32),
  812. .platform_data = dm365_isif_setup_pinmux,
  813. },
  814. };
  815. static struct resource dm365_osd_resources[] = {
  816. {
  817. .start = DM365_OSD_BASE,
  818. .end = DM365_OSD_BASE + 0xff,
  819. .flags = IORESOURCE_MEM,
  820. },
  821. };
  822. static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
  823. static struct platform_device dm365_osd_dev = {
  824. .name = DM365_VPBE_OSD_SUBDEV_NAME,
  825. .id = -1,
  826. .num_resources = ARRAY_SIZE(dm365_osd_resources),
  827. .resource = dm365_osd_resources,
  828. .dev = {
  829. .dma_mask = &dm365_video_dma_mask,
  830. .coherent_dma_mask = DMA_BIT_MASK(32),
  831. },
  832. };
  833. static struct resource dm365_venc_resources[] = {
  834. {
  835. .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
  836. .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
  837. .flags = IORESOURCE_IRQ,
  838. },
  839. /* venc registers io space */
  840. {
  841. .start = DM365_VENC_BASE,
  842. .end = DM365_VENC_BASE + 0x177,
  843. .flags = IORESOURCE_MEM,
  844. },
  845. /* vdaccfg registers io space */
  846. {
  847. .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
  848. .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
  849. .flags = IORESOURCE_MEM,
  850. },
  851. };
  852. static struct resource dm365_v4l2_disp_resources[] = {
  853. {
  854. .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
  855. .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
  856. .flags = IORESOURCE_IRQ,
  857. },
  858. /* venc registers io space */
  859. {
  860. .start = DM365_VENC_BASE,
  861. .end = DM365_VENC_BASE + 0x177,
  862. .flags = IORESOURCE_MEM,
  863. },
  864. };
  865. static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
  866. {
  867. switch (if_type) {
  868. case MEDIA_BUS_FMT_SGRBG8_1X8:
  869. davinci_cfg_reg(DM365_VOUT_FIELD_G81);
  870. davinci_cfg_reg(DM365_VOUT_COUTL_EN);
  871. davinci_cfg_reg(DM365_VOUT_COUTH_EN);
  872. break;
  873. case MEDIA_BUS_FMT_YUYV10_1X20:
  874. if (field)
  875. davinci_cfg_reg(DM365_VOUT_FIELD);
  876. else
  877. davinci_cfg_reg(DM365_VOUT_FIELD_G81);
  878. davinci_cfg_reg(DM365_VOUT_COUTL_EN);
  879. davinci_cfg_reg(DM365_VOUT_COUTH_EN);
  880. break;
  881. default:
  882. return -EINVAL;
  883. }
  884. return 0;
  885. }
  886. static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
  887. unsigned int pclock)
  888. {
  889. void __iomem *vpss_clkctl_reg;
  890. u32 val;
  891. vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
  892. switch (type) {
  893. case VPBE_ENC_STD:
  894. val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
  895. break;
  896. case VPBE_ENC_DV_TIMINGS:
  897. if (pclock <= 27000000) {
  898. val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
  899. } else {
  900. /* set sysclk4 to output 74.25 MHz from pll1 */
  901. val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
  902. VPSS_VENCCLKEN_ENABLE;
  903. }
  904. break;
  905. default:
  906. return -EINVAL;
  907. }
  908. writel(val, vpss_clkctl_reg);
  909. return 0;
  910. }
  911. static struct platform_device dm365_vpbe_display = {
  912. .name = "vpbe-v4l2",
  913. .id = -1,
  914. .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources),
  915. .resource = dm365_v4l2_disp_resources,
  916. .dev = {
  917. .dma_mask = &dm365_video_dma_mask,
  918. .coherent_dma_mask = DMA_BIT_MASK(32),
  919. },
  920. };
  921. static struct venc_platform_data dm365_venc_pdata = {
  922. .setup_pinmux = dm365_vpbe_setup_pinmux,
  923. .setup_clock = dm365_venc_setup_clock,
  924. };
  925. static struct platform_device dm365_venc_dev = {
  926. .name = DM365_VPBE_VENC_SUBDEV_NAME,
  927. .id = -1,
  928. .num_resources = ARRAY_SIZE(dm365_venc_resources),
  929. .resource = dm365_venc_resources,
  930. .dev = {
  931. .dma_mask = &dm365_video_dma_mask,
  932. .coherent_dma_mask = DMA_BIT_MASK(32),
  933. .platform_data = (void *)&dm365_venc_pdata,
  934. },
  935. };
  936. static struct platform_device dm365_vpbe_dev = {
  937. .name = "vpbe_controller",
  938. .id = -1,
  939. .dev = {
  940. .dma_mask = &dm365_video_dma_mask,
  941. .coherent_dma_mask = DMA_BIT_MASK(32),
  942. },
  943. };
  944. int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
  945. struct vpbe_config *vpbe_cfg)
  946. {
  947. if (vpfe_cfg || vpbe_cfg)
  948. platform_device_register(&dm365_vpss_device);
  949. if (vpfe_cfg) {
  950. vpfe_capture_dev.dev.platform_data = vpfe_cfg;
  951. platform_device_register(&dm365_isif_dev);
  952. platform_device_register(&vpfe_capture_dev);
  953. }
  954. if (vpbe_cfg) {
  955. dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
  956. platform_device_register(&dm365_osd_dev);
  957. platform_device_register(&dm365_venc_dev);
  958. platform_device_register(&dm365_vpbe_dev);
  959. platform_device_register(&dm365_vpbe_display);
  960. }
  961. return 0;
  962. }
  963. static const struct davinci_aintc_config dm365_aintc_config = {
  964. .reg = {
  965. .start = DAVINCI_ARM_INTC_BASE,
  966. .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
  967. .flags = IORESOURCE_MEM,
  968. },
  969. .num_irqs = 64,
  970. .prios = dm365_default_priorities,
  971. };
  972. void __init dm365_init_irq(void)
  973. {
  974. davinci_aintc_init(&dm365_aintc_config);
  975. }
  976. static int __init dm365_init_devices(void)
  977. {
  978. struct platform_device *edma_pdev;
  979. int ret = 0;
  980. if (!cpu_is_davinci_dm365())
  981. return 0;
  982. davinci_cfg_reg(DM365_INT_EDMA_CC);
  983. edma_pdev = platform_device_register_full(&dm365_edma_device);
  984. if (IS_ERR(edma_pdev)) {
  985. pr_warn("%s: Failed to register eDMA\n", __func__);
  986. return PTR_ERR(edma_pdev);
  987. }
  988. platform_device_register(&dm365_mdio_device);
  989. platform_device_register(&dm365_emac_device);
  990. ret = davinci_init_wdt();
  991. if (ret)
  992. pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
  993. return ret;
  994. }
  995. postcore_initcall(dm365_init_devices);