devices-da8xx.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * DA8XX/OMAP L1XX platform device data
  4. *
  5. * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
  6. * Derived from code that was:
  7. * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
  8. */
  9. #include <linux/ahci_platform.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/clk.h>
  12. #include <linux/clkdev.h>
  13. #include <linux/dma-map-ops.h>
  14. #include <linux/dmaengine.h>
  15. #include <linux/init.h>
  16. #include <linux/io.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/reboot.h>
  19. #include <linux/serial_8250.h>
  20. #include <mach/common.h>
  21. #include <mach/cputype.h>
  22. #include <mach/da8xx.h>
  23. #include "asp.h"
  24. #include "cpuidle.h"
  25. #include "irqs.h"
  26. #include "sram.h"
  27. #define DA8XX_TPCC_BASE 0x01c00000
  28. #define DA8XX_TPTC0_BASE 0x01c08000
  29. #define DA8XX_TPTC1_BASE 0x01c08400
  30. #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
  31. #define DA8XX_I2C0_BASE 0x01c22000
  32. #define DA8XX_RTC_BASE 0x01c23000
  33. #define DA8XX_PRUSS_MEM_BASE 0x01c30000
  34. #define DA8XX_MMCSD0_BASE 0x01c40000
  35. #define DA8XX_SPI0_BASE 0x01c41000
  36. #define DA830_SPI1_BASE 0x01e12000
  37. #define DA8XX_LCD_CNTRL_BASE 0x01e13000
  38. #define DA850_SATA_BASE 0x01e18000
  39. #define DA850_MMCSD1_BASE 0x01e1b000
  40. #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
  41. #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
  42. #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
  43. #define DA8XX_EMAC_MDIO_BASE 0x01e24000
  44. #define DA8XX_I2C1_BASE 0x01e28000
  45. #define DA850_TPCC1_BASE 0x01e30000
  46. #define DA850_TPTC2_BASE 0x01e38000
  47. #define DA850_SPI1_BASE 0x01f0e000
  48. #define DA8XX_DDR2_CTL_BASE 0xb0000000
  49. #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
  50. #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
  51. #define DA8XX_EMAC_RAM_OFFSET 0x0000
  52. #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
  53. void __iomem *da8xx_syscfg0_base;
  54. void __iomem *da8xx_syscfg1_base;
  55. static struct plat_serial8250_port da8xx_serial0_pdata[] = {
  56. {
  57. .mapbase = DA8XX_UART0_BASE,
  58. .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0),
  59. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  60. UPF_IOREMAP,
  61. .iotype = UPIO_MEM,
  62. .regshift = 2,
  63. },
  64. {
  65. .flags = 0,
  66. }
  67. };
  68. static struct plat_serial8250_port da8xx_serial1_pdata[] = {
  69. {
  70. .mapbase = DA8XX_UART1_BASE,
  71. .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1),
  72. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  73. UPF_IOREMAP,
  74. .iotype = UPIO_MEM,
  75. .regshift = 2,
  76. },
  77. {
  78. .flags = 0,
  79. }
  80. };
  81. static struct plat_serial8250_port da8xx_serial2_pdata[] = {
  82. {
  83. .mapbase = DA8XX_UART2_BASE,
  84. .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2),
  85. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  86. UPF_IOREMAP,
  87. .iotype = UPIO_MEM,
  88. .regshift = 2,
  89. },
  90. {
  91. .flags = 0,
  92. }
  93. };
  94. struct platform_device da8xx_serial_device[] = {
  95. {
  96. .name = "serial8250",
  97. .id = PLAT8250_DEV_PLATFORM,
  98. .dev = {
  99. .platform_data = da8xx_serial0_pdata,
  100. }
  101. },
  102. {
  103. .name = "serial8250",
  104. .id = PLAT8250_DEV_PLATFORM1,
  105. .dev = {
  106. .platform_data = da8xx_serial1_pdata,
  107. }
  108. },
  109. {
  110. .name = "serial8250",
  111. .id = PLAT8250_DEV_PLATFORM2,
  112. .dev = {
  113. .platform_data = da8xx_serial2_pdata,
  114. }
  115. },
  116. {
  117. }
  118. };
  119. static s8 da8xx_queue_priority_mapping[][2] = {
  120. /* {event queue no, Priority} */
  121. {0, 3},
  122. {1, 7},
  123. {-1, -1}
  124. };
  125. static s8 da850_queue_priority_mapping[][2] = {
  126. /* {event queue no, Priority} */
  127. {0, 3},
  128. {-1, -1}
  129. };
  130. static struct edma_soc_info da8xx_edma0_pdata = {
  131. .queue_priority_mapping = da8xx_queue_priority_mapping,
  132. .default_queue = EVENTQ_1,
  133. };
  134. static struct edma_soc_info da850_edma1_pdata = {
  135. .queue_priority_mapping = da850_queue_priority_mapping,
  136. .default_queue = EVENTQ_0,
  137. };
  138. static struct resource da8xx_edma0_resources[] = {
  139. {
  140. .name = "edma3_cc",
  141. .start = DA8XX_TPCC_BASE,
  142. .end = DA8XX_TPCC_BASE + SZ_32K - 1,
  143. .flags = IORESOURCE_MEM,
  144. },
  145. {
  146. .name = "edma3_tc0",
  147. .start = DA8XX_TPTC0_BASE,
  148. .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
  149. .flags = IORESOURCE_MEM,
  150. },
  151. {
  152. .name = "edma3_tc1",
  153. .start = DA8XX_TPTC1_BASE,
  154. .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
  155. .flags = IORESOURCE_MEM,
  156. },
  157. {
  158. .name = "edma3_ccint",
  159. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0),
  160. .flags = IORESOURCE_IRQ,
  161. },
  162. {
  163. .name = "edma3_ccerrint",
  164. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT),
  165. .flags = IORESOURCE_IRQ,
  166. },
  167. };
  168. static struct resource da850_edma1_resources[] = {
  169. {
  170. .name = "edma3_cc",
  171. .start = DA850_TPCC1_BASE,
  172. .end = DA850_TPCC1_BASE + SZ_32K - 1,
  173. .flags = IORESOURCE_MEM,
  174. },
  175. {
  176. .name = "edma3_tc0",
  177. .start = DA850_TPTC2_BASE,
  178. .end = DA850_TPTC2_BASE + SZ_1K - 1,
  179. .flags = IORESOURCE_MEM,
  180. },
  181. {
  182. .name = "edma3_ccint",
  183. .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1),
  184. .flags = IORESOURCE_IRQ,
  185. },
  186. {
  187. .name = "edma3_ccerrint",
  188. .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1),
  189. .flags = IORESOURCE_IRQ,
  190. },
  191. };
  192. static const struct platform_device_info da8xx_edma0_device __initconst = {
  193. .name = "edma",
  194. .id = 0,
  195. .dma_mask = DMA_BIT_MASK(32),
  196. .res = da8xx_edma0_resources,
  197. .num_res = ARRAY_SIZE(da8xx_edma0_resources),
  198. .data = &da8xx_edma0_pdata,
  199. .size_data = sizeof(da8xx_edma0_pdata),
  200. };
  201. static const struct platform_device_info da850_edma1_device __initconst = {
  202. .name = "edma",
  203. .id = 1,
  204. .dma_mask = DMA_BIT_MASK(32),
  205. .res = da850_edma1_resources,
  206. .num_res = ARRAY_SIZE(da850_edma1_resources),
  207. .data = &da850_edma1_pdata,
  208. .size_data = sizeof(da850_edma1_pdata),
  209. };
  210. static const struct dma_slave_map da830_edma_map[] = {
  211. { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
  212. { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
  213. { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
  214. { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
  215. { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
  216. { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
  217. { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
  218. { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
  219. { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
  220. { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
  221. { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
  222. { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
  223. };
  224. int __init da830_register_edma(struct edma_rsv_info *rsv)
  225. {
  226. struct platform_device *edma_pdev;
  227. da8xx_edma0_pdata.rsv = rsv;
  228. da8xx_edma0_pdata.slave_map = da830_edma_map;
  229. da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
  230. edma_pdev = platform_device_register_full(&da8xx_edma0_device);
  231. return PTR_ERR_OR_ZERO(edma_pdev);
  232. }
  233. static const struct dma_slave_map da850_edma0_map[] = {
  234. { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
  235. { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
  236. { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
  237. { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
  238. { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
  239. { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
  240. { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
  241. { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
  242. { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
  243. { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
  244. { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
  245. { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
  246. };
  247. static const struct dma_slave_map da850_edma1_map[] = {
  248. { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
  249. { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
  250. };
  251. int __init da850_register_edma(struct edma_rsv_info *rsv[2])
  252. {
  253. struct platform_device *edma_pdev;
  254. if (rsv) {
  255. da8xx_edma0_pdata.rsv = rsv[0];
  256. da850_edma1_pdata.rsv = rsv[1];
  257. }
  258. da8xx_edma0_pdata.slave_map = da850_edma0_map;
  259. da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
  260. edma_pdev = platform_device_register_full(&da8xx_edma0_device);
  261. if (IS_ERR(edma_pdev)) {
  262. pr_warn("%s: Failed to register eDMA0\n", __func__);
  263. return PTR_ERR(edma_pdev);
  264. }
  265. da850_edma1_pdata.slave_map = da850_edma1_map;
  266. da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
  267. edma_pdev = platform_device_register_full(&da850_edma1_device);
  268. return PTR_ERR_OR_ZERO(edma_pdev);
  269. }
  270. static struct resource da8xx_i2c_resources0[] = {
  271. {
  272. .start = DA8XX_I2C0_BASE,
  273. .end = DA8XX_I2C0_BASE + SZ_4K - 1,
  274. .flags = IORESOURCE_MEM,
  275. },
  276. {
  277. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
  278. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
  279. .flags = IORESOURCE_IRQ,
  280. },
  281. };
  282. static struct platform_device da8xx_i2c_device0 = {
  283. .name = "i2c_davinci",
  284. .id = 1,
  285. .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
  286. .resource = da8xx_i2c_resources0,
  287. };
  288. static struct resource da8xx_i2c_resources1[] = {
  289. {
  290. .start = DA8XX_I2C1_BASE,
  291. .end = DA8XX_I2C1_BASE + SZ_4K - 1,
  292. .flags = IORESOURCE_MEM,
  293. },
  294. {
  295. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
  296. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
  297. .flags = IORESOURCE_IRQ,
  298. },
  299. };
  300. static struct platform_device da8xx_i2c_device1 = {
  301. .name = "i2c_davinci",
  302. .id = 2,
  303. .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
  304. .resource = da8xx_i2c_resources1,
  305. };
  306. int __init da8xx_register_i2c(int instance,
  307. struct davinci_i2c_platform_data *pdata)
  308. {
  309. struct platform_device *pdev;
  310. if (instance == 0)
  311. pdev = &da8xx_i2c_device0;
  312. else if (instance == 1)
  313. pdev = &da8xx_i2c_device1;
  314. else
  315. return -EINVAL;
  316. pdev->dev.platform_data = pdata;
  317. return platform_device_register(pdev);
  318. }
  319. static struct resource da8xx_watchdog_resources[] = {
  320. {
  321. .start = DA8XX_WDOG_BASE,
  322. .end = DA8XX_WDOG_BASE + SZ_4K - 1,
  323. .flags = IORESOURCE_MEM,
  324. },
  325. };
  326. static struct platform_device da8xx_wdt_device = {
  327. .name = "davinci-wdt",
  328. .id = -1,
  329. .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
  330. .resource = da8xx_watchdog_resources,
  331. };
  332. int __init da8xx_register_watchdog(void)
  333. {
  334. return platform_device_register(&da8xx_wdt_device);
  335. }
  336. static struct resource da8xx_emac_resources[] = {
  337. {
  338. .start = DA8XX_EMAC_CPPI_PORT_BASE,
  339. .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
  340. .flags = IORESOURCE_MEM,
  341. },
  342. {
  343. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
  344. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
  345. .flags = IORESOURCE_IRQ,
  346. },
  347. {
  348. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
  349. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
  350. .flags = IORESOURCE_IRQ,
  351. },
  352. {
  353. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
  354. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
  355. .flags = IORESOURCE_IRQ,
  356. },
  357. {
  358. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
  359. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
  360. .flags = IORESOURCE_IRQ,
  361. },
  362. };
  363. struct emac_platform_data da8xx_emac_pdata = {
  364. .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
  365. .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
  366. .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
  367. .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
  368. .version = EMAC_VERSION_2,
  369. };
  370. static struct platform_device da8xx_emac_device = {
  371. .name = "davinci_emac",
  372. .id = 1,
  373. .dev = {
  374. .platform_data = &da8xx_emac_pdata,
  375. },
  376. .num_resources = ARRAY_SIZE(da8xx_emac_resources),
  377. .resource = da8xx_emac_resources,
  378. };
  379. static struct resource da8xx_mdio_resources[] = {
  380. {
  381. .start = DA8XX_EMAC_MDIO_BASE,
  382. .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
  383. .flags = IORESOURCE_MEM,
  384. },
  385. };
  386. static struct platform_device da8xx_mdio_device = {
  387. .name = "davinci_mdio",
  388. .id = 0,
  389. .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
  390. .resource = da8xx_mdio_resources,
  391. };
  392. int __init da8xx_register_emac(void)
  393. {
  394. int ret;
  395. ret = platform_device_register(&da8xx_mdio_device);
  396. if (ret < 0)
  397. return ret;
  398. return platform_device_register(&da8xx_emac_device);
  399. }
  400. static struct resource da830_mcasp1_resources[] = {
  401. {
  402. .name = "mpu",
  403. .start = DAVINCI_DA830_MCASP1_REG_BASE,
  404. .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
  405. .flags = IORESOURCE_MEM,
  406. },
  407. /* TX event */
  408. {
  409. .name = "tx",
  410. .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
  411. .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
  412. .flags = IORESOURCE_DMA,
  413. },
  414. /* RX event */
  415. {
  416. .name = "rx",
  417. .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
  418. .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
  419. .flags = IORESOURCE_DMA,
  420. },
  421. {
  422. .name = "common",
  423. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
  424. .flags = IORESOURCE_IRQ,
  425. },
  426. };
  427. static struct platform_device da830_mcasp1_device = {
  428. .name = "davinci-mcasp",
  429. .id = 1,
  430. .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
  431. .resource = da830_mcasp1_resources,
  432. };
  433. static struct resource da830_mcasp2_resources[] = {
  434. {
  435. .name = "mpu",
  436. .start = DAVINCI_DA830_MCASP2_REG_BASE,
  437. .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
  438. .flags = IORESOURCE_MEM,
  439. },
  440. /* TX event */
  441. {
  442. .name = "tx",
  443. .start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
  444. .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
  445. .flags = IORESOURCE_DMA,
  446. },
  447. /* RX event */
  448. {
  449. .name = "rx",
  450. .start = DAVINCI_DA830_DMA_MCASP2_AREVT,
  451. .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
  452. .flags = IORESOURCE_DMA,
  453. },
  454. {
  455. .name = "common",
  456. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
  457. .flags = IORESOURCE_IRQ,
  458. },
  459. };
  460. static struct platform_device da830_mcasp2_device = {
  461. .name = "davinci-mcasp",
  462. .id = 2,
  463. .num_resources = ARRAY_SIZE(da830_mcasp2_resources),
  464. .resource = da830_mcasp2_resources,
  465. };
  466. static struct resource da850_mcasp_resources[] = {
  467. {
  468. .name = "mpu",
  469. .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
  470. .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
  471. .flags = IORESOURCE_MEM,
  472. },
  473. /* TX event */
  474. {
  475. .name = "tx",
  476. .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
  477. .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
  478. .flags = IORESOURCE_DMA,
  479. },
  480. /* RX event */
  481. {
  482. .name = "rx",
  483. .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
  484. .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
  485. .flags = IORESOURCE_DMA,
  486. },
  487. {
  488. .name = "common",
  489. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
  490. .flags = IORESOURCE_IRQ,
  491. },
  492. };
  493. static struct platform_device da850_mcasp_device = {
  494. .name = "davinci-mcasp",
  495. .id = 0,
  496. .num_resources = ARRAY_SIZE(da850_mcasp_resources),
  497. .resource = da850_mcasp_resources,
  498. };
  499. void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
  500. {
  501. struct platform_device *pdev;
  502. switch (id) {
  503. case 0:
  504. /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
  505. pdev = &da850_mcasp_device;
  506. break;
  507. case 1:
  508. /* Valid for DA830/OMAP-L137 only */
  509. if (!cpu_is_davinci_da830())
  510. return;
  511. pdev = &da830_mcasp1_device;
  512. break;
  513. case 2:
  514. /* Valid for DA830/OMAP-L137 only */
  515. if (!cpu_is_davinci_da830())
  516. return;
  517. pdev = &da830_mcasp2_device;
  518. break;
  519. default:
  520. return;
  521. }
  522. pdev->dev.platform_data = pdata;
  523. platform_device_register(pdev);
  524. }
  525. static struct resource da8xx_pruss_resources[] = {
  526. {
  527. .start = DA8XX_PRUSS_MEM_BASE,
  528. .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
  529. .flags = IORESOURCE_MEM,
  530. },
  531. {
  532. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
  533. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
  534. .flags = IORESOURCE_IRQ,
  535. },
  536. {
  537. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
  538. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
  539. .flags = IORESOURCE_IRQ,
  540. },
  541. {
  542. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
  543. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
  544. .flags = IORESOURCE_IRQ,
  545. },
  546. {
  547. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
  548. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
  549. .flags = IORESOURCE_IRQ,
  550. },
  551. {
  552. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
  553. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
  554. .flags = IORESOURCE_IRQ,
  555. },
  556. {
  557. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
  558. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
  559. .flags = IORESOURCE_IRQ,
  560. },
  561. {
  562. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
  563. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
  564. .flags = IORESOURCE_IRQ,
  565. },
  566. {
  567. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
  568. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
  569. .flags = IORESOURCE_IRQ,
  570. },
  571. };
  572. static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
  573. .pintc_base = 0x4000,
  574. };
  575. static struct platform_device da8xx_uio_pruss_dev = {
  576. .name = "pruss_uio",
  577. .id = -1,
  578. .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
  579. .resource = da8xx_pruss_resources,
  580. .dev = {
  581. .coherent_dma_mask = DMA_BIT_MASK(32),
  582. .platform_data = &da8xx_uio_pruss_pdata,
  583. }
  584. };
  585. int __init da8xx_register_uio_pruss(void)
  586. {
  587. da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
  588. return platform_device_register(&da8xx_uio_pruss_dev);
  589. }
  590. static struct lcd_ctrl_config lcd_cfg = {
  591. .panel_shade = COLOR_ACTIVE,
  592. .bpp = 16,
  593. };
  594. struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
  595. .manu_name = "sharp",
  596. .controller_data = &lcd_cfg,
  597. .type = "Sharp_LCD035Q3DG01",
  598. };
  599. struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
  600. .manu_name = "sharp",
  601. .controller_data = &lcd_cfg,
  602. .type = "Sharp_LK043T1DG01",
  603. };
  604. static struct resource da8xx_lcdc_resources[] = {
  605. [0] = { /* registers */
  606. .start = DA8XX_LCD_CNTRL_BASE,
  607. .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
  608. .flags = IORESOURCE_MEM,
  609. },
  610. [1] = { /* interrupt */
  611. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
  612. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
  613. .flags = IORESOURCE_IRQ,
  614. },
  615. };
  616. static struct platform_device da8xx_lcdc_device = {
  617. .name = "da8xx_lcdc",
  618. .id = 0,
  619. .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
  620. .resource = da8xx_lcdc_resources,
  621. .dev = {
  622. .coherent_dma_mask = DMA_BIT_MASK(32),
  623. }
  624. };
  625. int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
  626. {
  627. da8xx_lcdc_device.dev.platform_data = pdata;
  628. return platform_device_register(&da8xx_lcdc_device);
  629. }
  630. static struct resource da8xx_gpio_resources[] = {
  631. { /* registers */
  632. .start = DA8XX_GPIO_BASE,
  633. .end = DA8XX_GPIO_BASE + SZ_4K - 1,
  634. .flags = IORESOURCE_MEM,
  635. },
  636. { /* interrupt */
  637. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
  638. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
  639. .flags = IORESOURCE_IRQ,
  640. },
  641. {
  642. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
  643. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
  644. .flags = IORESOURCE_IRQ,
  645. },
  646. {
  647. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
  648. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
  649. .flags = IORESOURCE_IRQ,
  650. },
  651. {
  652. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
  653. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
  654. .flags = IORESOURCE_IRQ,
  655. },
  656. {
  657. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
  658. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
  659. .flags = IORESOURCE_IRQ,
  660. },
  661. {
  662. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
  663. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
  664. .flags = IORESOURCE_IRQ,
  665. },
  666. {
  667. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
  668. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
  669. .flags = IORESOURCE_IRQ,
  670. },
  671. {
  672. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
  673. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
  674. .flags = IORESOURCE_IRQ,
  675. },
  676. {
  677. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
  678. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
  679. .flags = IORESOURCE_IRQ,
  680. },
  681. };
  682. static struct platform_device da8xx_gpio_device = {
  683. .name = "davinci_gpio",
  684. .id = -1,
  685. .num_resources = ARRAY_SIZE(da8xx_gpio_resources),
  686. .resource = da8xx_gpio_resources,
  687. };
  688. int __init da8xx_register_gpio(void *pdata)
  689. {
  690. da8xx_gpio_device.dev.platform_data = pdata;
  691. return platform_device_register(&da8xx_gpio_device);
  692. }
  693. static struct resource da8xx_mmcsd0_resources[] = {
  694. { /* registers */
  695. .start = DA8XX_MMCSD0_BASE,
  696. .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
  697. .flags = IORESOURCE_MEM,
  698. },
  699. { /* interrupt */
  700. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
  701. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
  702. .flags = IORESOURCE_IRQ,
  703. },
  704. };
  705. static struct platform_device da8xx_mmcsd0_device = {
  706. .name = "da830-mmc",
  707. .id = 0,
  708. .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
  709. .resource = da8xx_mmcsd0_resources,
  710. };
  711. int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
  712. {
  713. da8xx_mmcsd0_device.dev.platform_data = config;
  714. return platform_device_register(&da8xx_mmcsd0_device);
  715. }
  716. #ifdef CONFIG_ARCH_DAVINCI_DA850
  717. static struct resource da850_mmcsd1_resources[] = {
  718. { /* registers */
  719. .start = DA850_MMCSD1_BASE,
  720. .end = DA850_MMCSD1_BASE + SZ_4K - 1,
  721. .flags = IORESOURCE_MEM,
  722. },
  723. { /* interrupt */
  724. .start = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
  725. .end = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
  726. .flags = IORESOURCE_IRQ,
  727. },
  728. };
  729. static struct platform_device da850_mmcsd1_device = {
  730. .name = "da830-mmc",
  731. .id = 1,
  732. .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
  733. .resource = da850_mmcsd1_resources,
  734. };
  735. int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
  736. {
  737. da850_mmcsd1_device.dev.platform_data = config;
  738. return platform_device_register(&da850_mmcsd1_device);
  739. }
  740. #endif
  741. static struct resource da8xx_rproc_resources[] = {
  742. { /* DSP boot address */
  743. .name = "host1cfg",
  744. .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
  745. .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
  746. .flags = IORESOURCE_MEM,
  747. },
  748. { /* DSP interrupt registers */
  749. .name = "chipsig",
  750. .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
  751. .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
  752. .flags = IORESOURCE_MEM,
  753. },
  754. { /* DSP L2 RAM */
  755. .name = "l2sram",
  756. .start = DA8XX_DSP_L2_RAM_BASE,
  757. .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
  758. .flags = IORESOURCE_MEM,
  759. },
  760. { /* DSP L1P RAM */
  761. .name = "l1pram",
  762. .start = DA8XX_DSP_L1P_RAM_BASE,
  763. .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
  764. .flags = IORESOURCE_MEM,
  765. },
  766. { /* DSP L1D RAM */
  767. .name = "l1dram",
  768. .start = DA8XX_DSP_L1D_RAM_BASE,
  769. .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
  770. .flags = IORESOURCE_MEM,
  771. },
  772. { /* dsp irq */
  773. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
  774. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
  775. .flags = IORESOURCE_IRQ,
  776. },
  777. };
  778. static struct platform_device da8xx_dsp = {
  779. .name = "davinci-rproc",
  780. .dev = {
  781. .coherent_dma_mask = DMA_BIT_MASK(32),
  782. },
  783. .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
  784. .resource = da8xx_rproc_resources,
  785. };
  786. static bool rproc_mem_inited __initdata;
  787. #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
  788. static phys_addr_t rproc_base __initdata;
  789. static unsigned long rproc_size __initdata;
  790. static int __init early_rproc_mem(char *p)
  791. {
  792. char *endp;
  793. if (p == NULL)
  794. return 0;
  795. rproc_size = memparse(p, &endp);
  796. if (*endp == '@')
  797. rproc_base = memparse(endp + 1, NULL);
  798. return 0;
  799. }
  800. early_param("rproc_mem", early_rproc_mem);
  801. void __init da8xx_rproc_reserve_cma(void)
  802. {
  803. struct cma *cma;
  804. int ret;
  805. if (!rproc_base || !rproc_size) {
  806. pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
  807. " 'nn' and 'address' must both be non-zero\n",
  808. __func__);
  809. return;
  810. }
  811. pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
  812. __func__, rproc_size, (unsigned long)rproc_base);
  813. ret = dma_contiguous_reserve_area(rproc_size, rproc_base, 0, &cma,
  814. true);
  815. if (ret) {
  816. pr_err("%s: dma_contiguous_reserve_area failed %d\n",
  817. __func__, ret);
  818. return;
  819. }
  820. da8xx_dsp.dev.cma_area = cma;
  821. rproc_mem_inited = true;
  822. }
  823. #else
  824. void __init da8xx_rproc_reserve_cma(void)
  825. {
  826. }
  827. #endif
  828. int __init da8xx_register_rproc(void)
  829. {
  830. int ret;
  831. if (!rproc_mem_inited) {
  832. pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
  833. __func__);
  834. return -ENOMEM;
  835. }
  836. ret = platform_device_register(&da8xx_dsp);
  837. if (ret)
  838. pr_err("%s: can't register DSP device: %d\n", __func__, ret);
  839. return ret;
  840. };
  841. static struct resource da8xx_rtc_resources[] = {
  842. {
  843. .start = DA8XX_RTC_BASE,
  844. .end = DA8XX_RTC_BASE + SZ_4K - 1,
  845. .flags = IORESOURCE_MEM,
  846. },
  847. { /* timer irq */
  848. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
  849. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
  850. .flags = IORESOURCE_IRQ,
  851. },
  852. { /* alarm irq */
  853. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
  854. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
  855. .flags = IORESOURCE_IRQ,
  856. },
  857. };
  858. static struct platform_device da8xx_rtc_device = {
  859. .name = "da830-rtc",
  860. .id = -1,
  861. .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
  862. .resource = da8xx_rtc_resources,
  863. };
  864. int da8xx_register_rtc(void)
  865. {
  866. return platform_device_register(&da8xx_rtc_device);
  867. }
  868. static void __iomem *da8xx_ddr2_ctlr_base;
  869. void __iomem * __init da8xx_get_mem_ctlr(void)
  870. {
  871. if (da8xx_ddr2_ctlr_base)
  872. return da8xx_ddr2_ctlr_base;
  873. da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
  874. if (!da8xx_ddr2_ctlr_base)
  875. pr_warn("%s: Unable to map DDR2 controller", __func__);
  876. return da8xx_ddr2_ctlr_base;
  877. }
  878. static struct resource da8xx_cpuidle_resources[] = {
  879. {
  880. .start = DA8XX_DDR2_CTL_BASE,
  881. .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
  882. .flags = IORESOURCE_MEM,
  883. },
  884. };
  885. /* DA8XX devices support DDR2 power down */
  886. static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
  887. .ddr2_pdown = 1,
  888. };
  889. static struct platform_device da8xx_cpuidle_device = {
  890. .name = "cpuidle-davinci",
  891. .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
  892. .resource = da8xx_cpuidle_resources,
  893. .dev = {
  894. .platform_data = &da8xx_cpuidle_pdata,
  895. },
  896. };
  897. int __init da8xx_register_cpuidle(void)
  898. {
  899. da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
  900. return platform_device_register(&da8xx_cpuidle_device);
  901. }
  902. static struct resource da8xx_spi0_resources[] = {
  903. [0] = {
  904. .start = DA8XX_SPI0_BASE,
  905. .end = DA8XX_SPI0_BASE + SZ_4K - 1,
  906. .flags = IORESOURCE_MEM,
  907. },
  908. [1] = {
  909. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
  910. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
  911. .flags = IORESOURCE_IRQ,
  912. },
  913. };
  914. static struct resource da8xx_spi1_resources[] = {
  915. [0] = {
  916. .start = DA830_SPI1_BASE,
  917. .end = DA830_SPI1_BASE + SZ_4K - 1,
  918. .flags = IORESOURCE_MEM,
  919. },
  920. [1] = {
  921. .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
  922. .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
  923. .flags = IORESOURCE_IRQ,
  924. },
  925. };
  926. static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
  927. [0] = {
  928. .version = SPI_VERSION_2,
  929. .intr_line = 1,
  930. .dma_event_q = EVENTQ_0,
  931. .prescaler_limit = 2,
  932. },
  933. [1] = {
  934. .version = SPI_VERSION_2,
  935. .intr_line = 1,
  936. .dma_event_q = EVENTQ_0,
  937. .prescaler_limit = 2,
  938. },
  939. };
  940. static struct platform_device da8xx_spi_device[] = {
  941. [0] = {
  942. .name = "spi_davinci",
  943. .id = 0,
  944. .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
  945. .resource = da8xx_spi0_resources,
  946. .dev = {
  947. .platform_data = &da8xx_spi_pdata[0],
  948. },
  949. },
  950. [1] = {
  951. .name = "spi_davinci",
  952. .id = 1,
  953. .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
  954. .resource = da8xx_spi1_resources,
  955. .dev = {
  956. .platform_data = &da8xx_spi_pdata[1],
  957. },
  958. },
  959. };
  960. int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
  961. {
  962. if (instance < 0 || instance > 1)
  963. return -EINVAL;
  964. da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
  965. if (instance == 1 && cpu_is_davinci_da850()) {
  966. da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
  967. da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
  968. }
  969. return platform_device_register(&da8xx_spi_device[instance]);
  970. }
  971. #ifdef CONFIG_ARCH_DAVINCI_DA850
  972. int __init da850_register_sata_refclk(int rate)
  973. {
  974. struct clk *clk;
  975. clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate);
  976. if (IS_ERR(clk))
  977. return PTR_ERR(clk);
  978. return clk_register_clkdev(clk, "refclk", "ahci_da850");
  979. }
  980. static struct resource da850_sata_resources[] = {
  981. {
  982. .start = DA850_SATA_BASE,
  983. .end = DA850_SATA_BASE + 0x1fff,
  984. .flags = IORESOURCE_MEM,
  985. },
  986. {
  987. .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
  988. .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
  989. .flags = IORESOURCE_MEM,
  990. },
  991. {
  992. .start = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT),
  993. .flags = IORESOURCE_IRQ,
  994. },
  995. };
  996. static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
  997. static struct platform_device da850_sata_device = {
  998. .name = "ahci_da850",
  999. .id = -1,
  1000. .dev = {
  1001. .dma_mask = &da850_sata_dmamask,
  1002. .coherent_dma_mask = DMA_BIT_MASK(32),
  1003. },
  1004. .num_resources = ARRAY_SIZE(da850_sata_resources),
  1005. .resource = da850_sata_resources,
  1006. };
  1007. int __init da850_register_sata(unsigned long refclkpn)
  1008. {
  1009. int ret;
  1010. ret = da850_register_sata_refclk(refclkpn);
  1011. if (ret)
  1012. return ret;
  1013. return platform_device_register(&da850_sata_device);
  1014. }
  1015. #endif
  1016. static struct regmap *da8xx_cfgchip;
  1017. static const struct regmap_config da8xx_cfgchip_config __initconst = {
  1018. .name = "cfgchip",
  1019. .reg_bits = 32,
  1020. .val_bits = 32,
  1021. .reg_stride = 4,
  1022. .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG,
  1023. };
  1024. /**
  1025. * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
  1026. *
  1027. * This is for use on non-DT boards only. For DT boards, use
  1028. * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
  1029. *
  1030. * Returns: Pointer to the CFGCHIP regmap or negative error code.
  1031. */
  1032. struct regmap * __init da8xx_get_cfgchip(void)
  1033. {
  1034. if (IS_ERR_OR_NULL(da8xx_cfgchip))
  1035. da8xx_cfgchip = regmap_init_mmio(NULL,
  1036. DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG),
  1037. &da8xx_cfgchip_config);
  1038. return da8xx_cfgchip;
  1039. }