board-mityomapl138.c 14 KB

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  1. /*
  2. * Critical Link MityOMAP-L138 SoM
  3. *
  4. * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of
  8. * any kind, whether express or implied.
  9. */
  10. #define pr_fmt(fmt) "MityOMAPL138: " fmt
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/console.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/property.h>
  16. #include <linux/mtd/partitions.h>
  17. #include <linux/notifier.h>
  18. #include <linux/nvmem-consumer.h>
  19. #include <linux/nvmem-provider.h>
  20. #include <linux/regulator/machine.h>
  21. #include <linux/i2c.h>
  22. #include <linux/etherdevice.h>
  23. #include <linux/spi/spi.h>
  24. #include <linux/spi/flash.h>
  25. #include <asm/io.h>
  26. #include <asm/mach-types.h>
  27. #include <asm/mach/arch.h>
  28. #include <mach/common.h>
  29. #include <mach/da8xx.h>
  30. #include <linux/platform_data/mtd-davinci.h>
  31. #include <linux/platform_data/mtd-davinci-aemif.h>
  32. #include <linux/platform_data/ti-aemif.h>
  33. #include <mach/mux.h>
  34. #include <linux/platform_data/spi-davinci.h>
  35. #define MITYOMAPL138_PHY_ID ""
  36. #define FACTORY_CONFIG_MAGIC 0x012C0138
  37. #define FACTORY_CONFIG_VERSION 0x00010001
  38. /* Data Held in On-Board I2C device */
  39. struct factory_config {
  40. u32 magic;
  41. u32 version;
  42. u8 mac[6];
  43. u32 fpga_type;
  44. u32 spare;
  45. u32 serialnumber;
  46. char partnum[32];
  47. };
  48. static struct factory_config factory_config;
  49. #ifdef CONFIG_CPU_FREQ
  50. struct part_no_info {
  51. const char *part_no; /* part number string of interest */
  52. int max_freq; /* khz */
  53. };
  54. static struct part_no_info mityomapl138_pn_info[] = {
  55. {
  56. .part_no = "L138-C",
  57. .max_freq = 300000,
  58. },
  59. {
  60. .part_no = "L138-D",
  61. .max_freq = 375000,
  62. },
  63. {
  64. .part_no = "L138-F",
  65. .max_freq = 456000,
  66. },
  67. {
  68. .part_no = "1808-C",
  69. .max_freq = 300000,
  70. },
  71. {
  72. .part_no = "1808-D",
  73. .max_freq = 375000,
  74. },
  75. {
  76. .part_no = "1808-F",
  77. .max_freq = 456000,
  78. },
  79. {
  80. .part_no = "1810-D",
  81. .max_freq = 375000,
  82. },
  83. };
  84. static void mityomapl138_cpufreq_init(const char *partnum)
  85. {
  86. int i, ret;
  87. for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
  88. /*
  89. * the part number has additional characters beyond what is
  90. * stored in the table. This information is not needed for
  91. * determining the speed grade, and would require several
  92. * more table entries. Only check the first N characters
  93. * for a match.
  94. */
  95. if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
  96. strlen(mityomapl138_pn_info[i].part_no))) {
  97. da850_max_speed = mityomapl138_pn_info[i].max_freq;
  98. break;
  99. }
  100. }
  101. ret = da850_register_cpufreq("pll0_sysclk3");
  102. if (ret)
  103. pr_warn("cpufreq registration failed: %d\n", ret);
  104. }
  105. #else
  106. static void mityomapl138_cpufreq_init(const char *partnum) { }
  107. #endif
  108. static int read_factory_config(struct notifier_block *nb,
  109. unsigned long event, void *data)
  110. {
  111. int ret;
  112. const char *partnum = NULL;
  113. struct nvmem_device *nvmem = data;
  114. if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0)
  115. return NOTIFY_DONE;
  116. if (!IS_BUILTIN(CONFIG_NVMEM)) {
  117. pr_warn("Factory Config not available without CONFIG_NVMEM\n");
  118. goto bad_config;
  119. }
  120. ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
  121. &factory_config);
  122. if (ret != sizeof(struct factory_config)) {
  123. pr_warn("Read Factory Config Failed: %d\n", ret);
  124. goto bad_config;
  125. }
  126. if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
  127. pr_warn("Factory Config Magic Wrong (%X)\n",
  128. factory_config.magic);
  129. goto bad_config;
  130. }
  131. if (factory_config.version != FACTORY_CONFIG_VERSION) {
  132. pr_warn("Factory Config Version Wrong (%X)\n",
  133. factory_config.version);
  134. goto bad_config;
  135. }
  136. partnum = factory_config.partnum;
  137. pr_info("Part Number = %s\n", partnum);
  138. bad_config:
  139. /* default maximum speed is valid for all platforms */
  140. mityomapl138_cpufreq_init(partnum);
  141. return NOTIFY_STOP;
  142. }
  143. static struct notifier_block mityomapl138_nvmem_notifier = {
  144. .notifier_call = read_factory_config,
  145. };
  146. /*
  147. * We don't define a cell for factory config as it will be accessed from the
  148. * board file using the nvmem notifier chain.
  149. */
  150. static struct nvmem_cell_info mityomapl138_nvmem_cells[] = {
  151. {
  152. .name = "macaddr",
  153. .offset = 0x64,
  154. .bytes = ETH_ALEN,
  155. }
  156. };
  157. static struct nvmem_cell_table mityomapl138_nvmem_cell_table = {
  158. .nvmem_name = "1-00500",
  159. .cells = mityomapl138_nvmem_cells,
  160. .ncells = ARRAY_SIZE(mityomapl138_nvmem_cells),
  161. };
  162. static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = {
  163. .nvmem_name = "1-00500",
  164. .cell_name = "macaddr",
  165. .dev_id = "davinci_emac.1",
  166. .con_id = "mac-address",
  167. };
  168. static const struct property_entry mityomapl138_fd_chip_properties[] = {
  169. PROPERTY_ENTRY_U32("pagesize", 8),
  170. PROPERTY_ENTRY_BOOL("read-only"),
  171. { }
  172. };
  173. static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
  174. .bus_freq = 100, /* kHz */
  175. .bus_delay = 0, /* usec */
  176. };
  177. /* TPS65023 voltage regulator support */
  178. /* 1.2V Core */
  179. static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
  180. {
  181. .supply = "cvdd",
  182. },
  183. };
  184. /* 1.8V */
  185. static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
  186. {
  187. .supply = "usb0_vdda18",
  188. },
  189. {
  190. .supply = "usb1_vdda18",
  191. },
  192. {
  193. .supply = "ddr_dvdd18",
  194. },
  195. {
  196. .supply = "sata_vddr",
  197. },
  198. };
  199. /* 1.2V */
  200. static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
  201. {
  202. .supply = "sata_vdd",
  203. },
  204. {
  205. .supply = "usb_cvdd",
  206. },
  207. {
  208. .supply = "pll0_vdda",
  209. },
  210. {
  211. .supply = "pll1_vdda",
  212. },
  213. };
  214. /* 1.8V Aux LDO, not used */
  215. static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
  216. {
  217. .supply = "1.8v_aux",
  218. },
  219. };
  220. /* FPGA VCC Aux (2.5 or 3.3) LDO */
  221. static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
  222. {
  223. .supply = "vccaux",
  224. },
  225. };
  226. static struct regulator_init_data tps65023_regulator_data[] = {
  227. /* dcdc1 */
  228. {
  229. .constraints = {
  230. .min_uV = 1150000,
  231. .max_uV = 1350000,
  232. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
  233. REGULATOR_CHANGE_STATUS,
  234. .boot_on = 1,
  235. },
  236. .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
  237. .consumer_supplies = tps65023_dcdc1_consumers,
  238. },
  239. /* dcdc2 */
  240. {
  241. .constraints = {
  242. .min_uV = 1800000,
  243. .max_uV = 1800000,
  244. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  245. .boot_on = 1,
  246. },
  247. .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
  248. .consumer_supplies = tps65023_dcdc2_consumers,
  249. },
  250. /* dcdc3 */
  251. {
  252. .constraints = {
  253. .min_uV = 1200000,
  254. .max_uV = 1200000,
  255. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  256. .boot_on = 1,
  257. },
  258. .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
  259. .consumer_supplies = tps65023_dcdc3_consumers,
  260. },
  261. /* ldo1 */
  262. {
  263. .constraints = {
  264. .min_uV = 1800000,
  265. .max_uV = 1800000,
  266. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  267. .boot_on = 1,
  268. },
  269. .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
  270. .consumer_supplies = tps65023_ldo1_consumers,
  271. },
  272. /* ldo2 */
  273. {
  274. .constraints = {
  275. .min_uV = 2500000,
  276. .max_uV = 3300000,
  277. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
  278. REGULATOR_CHANGE_STATUS,
  279. .boot_on = 1,
  280. },
  281. .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
  282. .consumer_supplies = tps65023_ldo2_consumers,
  283. },
  284. };
  285. static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
  286. {
  287. I2C_BOARD_INFO("tps65023", 0x48),
  288. .platform_data = &tps65023_regulator_data[0],
  289. },
  290. {
  291. I2C_BOARD_INFO("24c02", 0x50),
  292. .properties = mityomapl138_fd_chip_properties,
  293. },
  294. };
  295. static int __init pmic_tps65023_init(void)
  296. {
  297. return i2c_register_board_info(1, mityomap_tps65023_info,
  298. ARRAY_SIZE(mityomap_tps65023_info));
  299. }
  300. /*
  301. * SPI Devices:
  302. * SPI1_CS0: 8M Flash ST-M25P64-VME6G
  303. */
  304. static struct mtd_partition spi_flash_partitions[] = {
  305. [0] = {
  306. .name = "ubl",
  307. .offset = 0,
  308. .size = SZ_64K,
  309. .mask_flags = MTD_WRITEABLE,
  310. },
  311. [1] = {
  312. .name = "u-boot",
  313. .offset = MTDPART_OFS_APPEND,
  314. .size = SZ_512K,
  315. .mask_flags = MTD_WRITEABLE,
  316. },
  317. [2] = {
  318. .name = "u-boot-env",
  319. .offset = MTDPART_OFS_APPEND,
  320. .size = SZ_64K,
  321. .mask_flags = MTD_WRITEABLE,
  322. },
  323. [3] = {
  324. .name = "periph-config",
  325. .offset = MTDPART_OFS_APPEND,
  326. .size = SZ_64K,
  327. .mask_flags = MTD_WRITEABLE,
  328. },
  329. [4] = {
  330. .name = "reserved",
  331. .offset = MTDPART_OFS_APPEND,
  332. .size = SZ_256K + SZ_64K,
  333. },
  334. [5] = {
  335. .name = "kernel",
  336. .offset = MTDPART_OFS_APPEND,
  337. .size = SZ_2M + SZ_1M,
  338. },
  339. [6] = {
  340. .name = "fpga",
  341. .offset = MTDPART_OFS_APPEND,
  342. .size = SZ_2M,
  343. },
  344. [7] = {
  345. .name = "spare",
  346. .offset = MTDPART_OFS_APPEND,
  347. .size = MTDPART_SIZ_FULL,
  348. },
  349. };
  350. static struct flash_platform_data mityomapl138_spi_flash_data = {
  351. .name = "m25p80",
  352. .parts = spi_flash_partitions,
  353. .nr_parts = ARRAY_SIZE(spi_flash_partitions),
  354. .type = "m24p64",
  355. };
  356. static struct davinci_spi_config spi_eprom_config = {
  357. .io_type = SPI_IO_TYPE_DMA,
  358. .c2tdelay = 8,
  359. .t2cdelay = 8,
  360. };
  361. static struct spi_board_info mityomapl138_spi_flash_info[] = {
  362. {
  363. .modalias = "m25p80",
  364. .platform_data = &mityomapl138_spi_flash_data,
  365. .controller_data = &spi_eprom_config,
  366. .mode = SPI_MODE_0,
  367. .max_speed_hz = 30000000,
  368. .bus_num = 1,
  369. .chip_select = 0,
  370. },
  371. };
  372. /*
  373. * MityDSP-L138 includes a 256 MByte large-page NAND flash
  374. * (128K blocks).
  375. */
  376. static struct mtd_partition mityomapl138_nandflash_partition[] = {
  377. {
  378. .name = "rootfs",
  379. .offset = 0,
  380. .size = SZ_128M,
  381. .mask_flags = 0, /* MTD_WRITEABLE, */
  382. },
  383. {
  384. .name = "homefs",
  385. .offset = MTDPART_OFS_APPEND,
  386. .size = MTDPART_SIZ_FULL,
  387. .mask_flags = 0,
  388. },
  389. };
  390. static struct davinci_nand_pdata mityomapl138_nandflash_data = {
  391. .core_chipsel = 1,
  392. .parts = mityomapl138_nandflash_partition,
  393. .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
  394. .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
  395. .bbt_options = NAND_BBT_USE_FLASH,
  396. .options = NAND_BUSWIDTH_16,
  397. .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
  398. };
  399. static struct resource mityomapl138_nandflash_resource[] = {
  400. {
  401. .start = DA8XX_AEMIF_CS3_BASE,
  402. .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
  403. .flags = IORESOURCE_MEM,
  404. },
  405. {
  406. .start = DA8XX_AEMIF_CTL_BASE,
  407. .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
  408. .flags = IORESOURCE_MEM,
  409. },
  410. };
  411. static struct platform_device mityomapl138_aemif_devices[] = {
  412. {
  413. .name = "davinci_nand",
  414. .id = 1,
  415. .dev = {
  416. .platform_data = &mityomapl138_nandflash_data,
  417. },
  418. .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
  419. .resource = mityomapl138_nandflash_resource,
  420. },
  421. };
  422. static struct resource mityomapl138_aemif_resources[] = {
  423. {
  424. .start = DA8XX_AEMIF_CTL_BASE,
  425. .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
  426. .flags = IORESOURCE_MEM,
  427. },
  428. };
  429. static struct aemif_abus_data mityomapl138_aemif_abus_data[] = {
  430. {
  431. .cs = 1,
  432. },
  433. };
  434. static struct aemif_platform_data mityomapl138_aemif_pdata = {
  435. .abus_data = mityomapl138_aemif_abus_data,
  436. .num_abus_data = ARRAY_SIZE(mityomapl138_aemif_abus_data),
  437. .sub_devices = mityomapl138_aemif_devices,
  438. .num_sub_devices = ARRAY_SIZE(mityomapl138_aemif_devices),
  439. };
  440. static struct platform_device mityomapl138_aemif_device = {
  441. .name = "ti-aemif",
  442. .id = -1,
  443. .dev = {
  444. .platform_data = &mityomapl138_aemif_pdata,
  445. },
  446. .resource = mityomapl138_aemif_resources,
  447. .num_resources = ARRAY_SIZE(mityomapl138_aemif_resources),
  448. };
  449. static void __init mityomapl138_setup_nand(void)
  450. {
  451. if (platform_device_register(&mityomapl138_aemif_device))
  452. pr_warn("%s: Cannot register AEMIF device\n", __func__);
  453. }
  454. static const short mityomap_mii_pins[] = {
  455. DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
  456. DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
  457. DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
  458. DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
  459. DA850_MDIO_D,
  460. -1
  461. };
  462. static const short mityomap_rmii_pins[] = {
  463. DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
  464. DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
  465. DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
  466. DA850_MDIO_D,
  467. -1
  468. };
  469. static void __init mityomapl138_config_emac(void)
  470. {
  471. void __iomem *cfg_chip3_base;
  472. int ret;
  473. u32 val;
  474. struct davinci_soc_info *soc_info = &davinci_soc_info;
  475. soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
  476. cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
  477. val = __raw_readl(cfg_chip3_base);
  478. if (soc_info->emac_pdata->rmii_en) {
  479. val |= BIT(8);
  480. ret = davinci_cfg_reg_list(mityomap_rmii_pins);
  481. pr_info("RMII PHY configured\n");
  482. } else {
  483. val &= ~BIT(8);
  484. ret = davinci_cfg_reg_list(mityomap_mii_pins);
  485. pr_info("MII PHY configured\n");
  486. }
  487. if (ret) {
  488. pr_warn("mii/rmii mux setup failed: %d\n", ret);
  489. return;
  490. }
  491. /* configure the CFGCHIP3 register for RMII or MII */
  492. __raw_writel(val, cfg_chip3_base);
  493. soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
  494. ret = da8xx_register_emac();
  495. if (ret)
  496. pr_warn("emac registration failed: %d\n", ret);
  497. }
  498. static void __init mityomapl138_init(void)
  499. {
  500. int ret;
  501. da850_register_clocks();
  502. /* for now, no special EDMA channels are reserved */
  503. ret = da850_register_edma(NULL);
  504. if (ret)
  505. pr_warn("edma registration failed: %d\n", ret);
  506. ret = da8xx_register_watchdog();
  507. if (ret)
  508. pr_warn("watchdog registration failed: %d\n", ret);
  509. davinci_serial_init(da8xx_serial_device);
  510. nvmem_register_notifier(&mityomapl138_nvmem_notifier);
  511. nvmem_add_cell_table(&mityomapl138_nvmem_cell_table);
  512. nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1);
  513. ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
  514. if (ret)
  515. pr_warn("i2c0 registration failed: %d\n", ret);
  516. ret = pmic_tps65023_init();
  517. if (ret)
  518. pr_warn("TPS65023 PMIC init failed: %d\n", ret);
  519. mityomapl138_setup_nand();
  520. ret = spi_register_board_info(mityomapl138_spi_flash_info,
  521. ARRAY_SIZE(mityomapl138_spi_flash_info));
  522. if (ret)
  523. pr_warn("spi info registration failed: %d\n", ret);
  524. ret = da8xx_register_spi_bus(1,
  525. ARRAY_SIZE(mityomapl138_spi_flash_info));
  526. if (ret)
  527. pr_warn("spi 1 registration failed: %d\n", ret);
  528. mityomapl138_config_emac();
  529. ret = da8xx_register_rtc();
  530. if (ret)
  531. pr_warn("rtc setup failed: %d\n", ret);
  532. ret = da8xx_register_cpuidle();
  533. if (ret)
  534. pr_warn("cpuidle registration failed: %d\n", ret);
  535. davinci_pm_init();
  536. }
  537. #ifdef CONFIG_SERIAL_8250_CONSOLE
  538. static int __init mityomapl138_console_init(void)
  539. {
  540. if (!machine_is_mityomapl138())
  541. return 0;
  542. return add_preferred_console("ttyS", 1, "115200");
  543. }
  544. console_initcall(mityomapl138_console_init);
  545. #endif
  546. static void __init mityomapl138_map_io(void)
  547. {
  548. da850_init();
  549. }
  550. MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
  551. .atag_offset = 0x100,
  552. .map_io = mityomapl138_map_io,
  553. .init_irq = da850_init_irq,
  554. .init_time = da850_init_time,
  555. .init_machine = mityomapl138_init,
  556. .init_late = davinci_init_late,
  557. .dma_zone_size = SZ_128M,
  558. MACHINE_END