board-dm365-evm.c 20 KB

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  1. /*
  2. * TI DaVinci DM365 EVM board support
  3. *
  4. * Copyright (C) 2009 Texas Instruments Incorporated
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/err.h>
  18. #include <linux/i2c.h>
  19. #include <linux/io.h>
  20. #include <linux/clk.h>
  21. #include <linux/property.h>
  22. #include <linux/leds.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/partitions.h>
  25. #include <linux/slab.h>
  26. #include <linux/mtd/rawnand.h>
  27. #include <linux/nvmem-provider.h>
  28. #include <linux/input.h>
  29. #include <linux/spi/spi.h>
  30. #include <linux/spi/eeprom.h>
  31. #include <linux/v4l2-dv-timings.h>
  32. #include <linux/platform_data/ti-aemif.h>
  33. #include <linux/regulator/fixed.h>
  34. #include <linux/regulator/machine.h>
  35. #include <asm/mach-types.h>
  36. #include <asm/mach/arch.h>
  37. #include <mach/mux.h>
  38. #include <mach/common.h>
  39. #include <linux/platform_data/i2c-davinci.h>
  40. #include <mach/serial.h>
  41. #include <linux/platform_data/mmc-davinci.h>
  42. #include <linux/platform_data/mtd-davinci.h>
  43. #include <linux/platform_data/keyscan-davinci.h>
  44. #include <media/i2c/ths7303.h>
  45. #include <media/i2c/tvp514x.h>
  46. #include "davinci.h"
  47. static inline int have_imager(void)
  48. {
  49. /* REVISIT when it's supported, trigger via Kconfig */
  50. return 0;
  51. }
  52. static inline int have_tvp7002(void)
  53. {
  54. /* REVISIT when it's supported, trigger via Kconfig */
  55. return 0;
  56. }
  57. #define DM365_EVM_PHY_ID "davinci_mdio-0:01"
  58. /*
  59. * A MAX-II CPLD is used for various board control functions.
  60. */
  61. #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
  62. #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
  63. #define CPLD_TEST CPLD_OFFSET(0,1)
  64. #define CPLD_LEDS CPLD_OFFSET(0,2)
  65. #define CPLD_MUX CPLD_OFFSET(0,3)
  66. #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
  67. #define CPLD_POWER CPLD_OFFSET(1,1)
  68. #define CPLD_VIDEO CPLD_OFFSET(1,2)
  69. #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
  70. #define CPLD_DILC_OUT CPLD_OFFSET(2,0)
  71. #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
  72. #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
  73. #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
  74. #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
  75. #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
  76. #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
  77. #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
  78. #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
  79. #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
  80. #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
  81. #define CPLD_RESETS CPLD_OFFSET(4,3)
  82. #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
  83. #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
  84. #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
  85. #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
  86. #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
  87. #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
  88. static void __iomem *cpld;
  89. /* NOTE: this is geared for the standard config, with a socketed
  90. * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
  91. * swap chips with a different block size, partitioning will
  92. * need to be changed. This NAND chip MT29F16G08FAA is the default
  93. * NAND shipped with the Spectrum Digital DM365 EVM
  94. */
  95. #define NAND_BLOCK_SIZE SZ_128K
  96. static struct mtd_partition davinci_nand_partitions[] = {
  97. {
  98. /* UBL (a few copies) plus U-Boot */
  99. .name = "bootloader",
  100. .offset = 0,
  101. .size = 30 * NAND_BLOCK_SIZE,
  102. .mask_flags = MTD_WRITEABLE, /* force read-only */
  103. }, {
  104. /* U-Boot environment */
  105. .name = "params",
  106. .offset = MTDPART_OFS_APPEND,
  107. .size = 2 * NAND_BLOCK_SIZE,
  108. .mask_flags = 0,
  109. }, {
  110. .name = "kernel",
  111. .offset = MTDPART_OFS_APPEND,
  112. .size = SZ_4M,
  113. .mask_flags = 0,
  114. }, {
  115. .name = "filesystem1",
  116. .offset = MTDPART_OFS_APPEND,
  117. .size = SZ_512M,
  118. .mask_flags = 0,
  119. }, {
  120. .name = "filesystem2",
  121. .offset = MTDPART_OFS_APPEND,
  122. .size = MTDPART_SIZ_FULL,
  123. .mask_flags = 0,
  124. }
  125. /* two blocks with bad block table (and mirror) at the end */
  126. };
  127. static struct davinci_nand_pdata davinci_nand_data = {
  128. .core_chipsel = 0,
  129. .mask_chipsel = BIT(14),
  130. .parts = davinci_nand_partitions,
  131. .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
  132. .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
  133. .bbt_options = NAND_BBT_USE_FLASH,
  134. .ecc_bits = 4,
  135. };
  136. static struct resource davinci_nand_resources[] = {
  137. {
  138. .start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
  139. .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
  140. .flags = IORESOURCE_MEM,
  141. }, {
  142. .start = DM365_ASYNC_EMIF_CONTROL_BASE,
  143. .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
  144. .flags = IORESOURCE_MEM,
  145. },
  146. };
  147. static struct platform_device davinci_aemif_devices[] = {
  148. {
  149. .name = "davinci_nand",
  150. .id = 0,
  151. .num_resources = ARRAY_SIZE(davinci_nand_resources),
  152. .resource = davinci_nand_resources,
  153. .dev = {
  154. .platform_data = &davinci_nand_data,
  155. },
  156. }
  157. };
  158. static struct resource davinci_aemif_resources[] = {
  159. {
  160. .start = DM365_ASYNC_EMIF_CONTROL_BASE,
  161. .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
  162. .flags = IORESOURCE_MEM,
  163. },
  164. };
  165. static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
  166. {
  167. .cs = 1,
  168. },
  169. };
  170. static struct aemif_platform_data davinci_aemif_pdata = {
  171. .abus_data = da850_evm_aemif_abus_data,
  172. .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data),
  173. .sub_devices = davinci_aemif_devices,
  174. .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices),
  175. };
  176. static struct platform_device davinci_aemif_device = {
  177. .name = "ti-aemif",
  178. .id = -1,
  179. .dev = {
  180. .platform_data = &davinci_aemif_pdata,
  181. },
  182. .resource = davinci_aemif_resources,
  183. .num_resources = ARRAY_SIZE(davinci_aemif_resources),
  184. };
  185. static struct nvmem_cell_info davinci_nvmem_cells[] = {
  186. {
  187. .name = "macaddr",
  188. .offset = 0x7f00,
  189. .bytes = ETH_ALEN,
  190. }
  191. };
  192. static struct nvmem_cell_table davinci_nvmem_cell_table = {
  193. .nvmem_name = "1-00500",
  194. .cells = davinci_nvmem_cells,
  195. .ncells = ARRAY_SIZE(davinci_nvmem_cells),
  196. };
  197. static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = {
  198. .nvmem_name = "1-00500",
  199. .cell_name = "macaddr",
  200. .dev_id = "davinci_emac.1",
  201. .con_id = "mac-address",
  202. };
  203. static const struct property_entry eeprom_properties[] = {
  204. PROPERTY_ENTRY_U32("pagesize", 64),
  205. { }
  206. };
  207. static struct i2c_board_info i2c_info[] = {
  208. {
  209. I2C_BOARD_INFO("24c256", 0x50),
  210. .properties = eeprom_properties,
  211. },
  212. {
  213. I2C_BOARD_INFO("tlv320aic3x", 0x18),
  214. },
  215. };
  216. static struct davinci_i2c_platform_data i2c_pdata = {
  217. .bus_freq = 400 /* kHz */,
  218. .bus_delay = 0 /* usec */,
  219. };
  220. /* Fixed regulator support */
  221. static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
  222. /* Baseboard 3.3V: 5V -> TPS767D301 -> 3.3V */
  223. REGULATOR_SUPPLY("AVDD", "1-0018"),
  224. REGULATOR_SUPPLY("DRVDD", "1-0018"),
  225. REGULATOR_SUPPLY("IOVDD", "1-0018"),
  226. };
  227. static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
  228. /* Baseboard 1.8V: 5V -> TPS767D301 -> 1.8V */
  229. REGULATOR_SUPPLY("DVDD", "1-0018"),
  230. };
  231. static int dm365evm_keyscan_enable(struct device *dev)
  232. {
  233. return davinci_cfg_reg(DM365_KEYSCAN);
  234. }
  235. static unsigned short dm365evm_keymap[] = {
  236. KEY_KP2,
  237. KEY_LEFT,
  238. KEY_EXIT,
  239. KEY_DOWN,
  240. KEY_ENTER,
  241. KEY_UP,
  242. KEY_KP1,
  243. KEY_RIGHT,
  244. KEY_MENU,
  245. KEY_RECORD,
  246. KEY_REWIND,
  247. KEY_KPMINUS,
  248. KEY_STOP,
  249. KEY_FASTFORWARD,
  250. KEY_KPPLUS,
  251. KEY_PLAYPAUSE,
  252. 0
  253. };
  254. static struct davinci_ks_platform_data dm365evm_ks_data = {
  255. .device_enable = dm365evm_keyscan_enable,
  256. .keymap = dm365evm_keymap,
  257. .keymapsize = ARRAY_SIZE(dm365evm_keymap),
  258. .rep = 1,
  259. /* Scan period = strobe + interval */
  260. .strobe = 0x5,
  261. .interval = 0x2,
  262. .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
  263. };
  264. static int cpld_mmc_get_cd(int module)
  265. {
  266. if (!cpld)
  267. return -ENXIO;
  268. /* low == card present */
  269. return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
  270. }
  271. static int cpld_mmc_get_ro(int module)
  272. {
  273. if (!cpld)
  274. return -ENXIO;
  275. /* high == card's write protect switch active */
  276. return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
  277. }
  278. static struct davinci_mmc_config dm365evm_mmc_config = {
  279. .get_cd = cpld_mmc_get_cd,
  280. .get_ro = cpld_mmc_get_ro,
  281. .wires = 4,
  282. .max_freq = 50000000,
  283. .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
  284. };
  285. static void dm365evm_emac_configure(void)
  286. {
  287. /*
  288. * EMAC pins are multiplexed with GPIO and UART
  289. * Further details are available at the DM365 ARM
  290. * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
  291. */
  292. davinci_cfg_reg(DM365_EMAC_TX_EN);
  293. davinci_cfg_reg(DM365_EMAC_TX_CLK);
  294. davinci_cfg_reg(DM365_EMAC_COL);
  295. davinci_cfg_reg(DM365_EMAC_TXD3);
  296. davinci_cfg_reg(DM365_EMAC_TXD2);
  297. davinci_cfg_reg(DM365_EMAC_TXD1);
  298. davinci_cfg_reg(DM365_EMAC_TXD0);
  299. davinci_cfg_reg(DM365_EMAC_RXD3);
  300. davinci_cfg_reg(DM365_EMAC_RXD2);
  301. davinci_cfg_reg(DM365_EMAC_RXD1);
  302. davinci_cfg_reg(DM365_EMAC_RXD0);
  303. davinci_cfg_reg(DM365_EMAC_RX_CLK);
  304. davinci_cfg_reg(DM365_EMAC_RX_DV);
  305. davinci_cfg_reg(DM365_EMAC_RX_ER);
  306. davinci_cfg_reg(DM365_EMAC_CRS);
  307. davinci_cfg_reg(DM365_EMAC_MDIO);
  308. davinci_cfg_reg(DM365_EMAC_MDCLK);
  309. /*
  310. * EMAC interrupts are multiplexed with GPIO interrupts
  311. * Details are available at the DM365 ARM
  312. * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
  313. */
  314. davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
  315. davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
  316. davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
  317. davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
  318. }
  319. static void dm365evm_mmc_configure(void)
  320. {
  321. /*
  322. * MMC/SD pins are multiplexed with GPIO and EMIF
  323. * Further details are available at the DM365 ARM
  324. * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
  325. */
  326. davinci_cfg_reg(DM365_SD1_CLK);
  327. davinci_cfg_reg(DM365_SD1_CMD);
  328. davinci_cfg_reg(DM365_SD1_DATA3);
  329. davinci_cfg_reg(DM365_SD1_DATA2);
  330. davinci_cfg_reg(DM365_SD1_DATA1);
  331. davinci_cfg_reg(DM365_SD1_DATA0);
  332. }
  333. static struct tvp514x_platform_data tvp5146_pdata = {
  334. .clk_polarity = 0,
  335. .hs_polarity = 1,
  336. .vs_polarity = 1
  337. };
  338. #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
  339. /* Inputs available at the TVP5146 */
  340. static struct v4l2_input tvp5146_inputs[] = {
  341. {
  342. .index = 0,
  343. .name = "Composite",
  344. .type = V4L2_INPUT_TYPE_CAMERA,
  345. .std = TVP514X_STD_ALL,
  346. },
  347. {
  348. .index = 1,
  349. .name = "S-Video",
  350. .type = V4L2_INPUT_TYPE_CAMERA,
  351. .std = TVP514X_STD_ALL,
  352. },
  353. };
  354. /*
  355. * this is the route info for connecting each input to decoder
  356. * ouput that goes to vpfe. There is a one to one correspondence
  357. * with tvp5146_inputs
  358. */
  359. static struct vpfe_route tvp5146_routes[] = {
  360. {
  361. .input = INPUT_CVBS_VI2B,
  362. .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
  363. },
  364. {
  365. .input = INPUT_SVIDEO_VI2C_VI1C,
  366. .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
  367. },
  368. };
  369. static struct vpfe_subdev_info vpfe_sub_devs[] = {
  370. {
  371. .name = "tvp5146",
  372. .grp_id = 0,
  373. .num_inputs = ARRAY_SIZE(tvp5146_inputs),
  374. .inputs = tvp5146_inputs,
  375. .routes = tvp5146_routes,
  376. .can_route = 1,
  377. .ccdc_if_params = {
  378. .if_type = VPFE_BT656,
  379. .hdpol = VPFE_PINPOL_POSITIVE,
  380. .vdpol = VPFE_PINPOL_POSITIVE,
  381. },
  382. .board_info = {
  383. I2C_BOARD_INFO("tvp5146", 0x5d),
  384. .platform_data = &tvp5146_pdata,
  385. },
  386. },
  387. };
  388. static struct vpfe_config vpfe_cfg = {
  389. .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
  390. .sub_devs = vpfe_sub_devs,
  391. .i2c_adapter_id = 1,
  392. .card_name = "DM365 EVM",
  393. .ccdc = "ISIF",
  394. };
  395. /* venc standards timings */
  396. static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
  397. {
  398. .name = "ntsc",
  399. .timings_type = VPBE_ENC_STD,
  400. .std_id = V4L2_STD_NTSC,
  401. .interlaced = 1,
  402. .xres = 720,
  403. .yres = 480,
  404. .aspect = {11, 10},
  405. .fps = {30000, 1001},
  406. .left_margin = 0x79,
  407. .upper_margin = 0x10,
  408. },
  409. {
  410. .name = "pal",
  411. .timings_type = VPBE_ENC_STD,
  412. .std_id = V4L2_STD_PAL,
  413. .interlaced = 1,
  414. .xres = 720,
  415. .yres = 576,
  416. .aspect = {54, 59},
  417. .fps = {25, 1},
  418. .left_margin = 0x7E,
  419. .upper_margin = 0x16,
  420. },
  421. };
  422. /* venc dv timings */
  423. static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
  424. {
  425. .name = "480p59_94",
  426. .timings_type = VPBE_ENC_DV_TIMINGS,
  427. .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
  428. .interlaced = 0,
  429. .xres = 720,
  430. .yres = 480,
  431. .aspect = {1, 1},
  432. .fps = {5994, 100},
  433. .left_margin = 0x8F,
  434. .upper_margin = 0x2D,
  435. },
  436. {
  437. .name = "576p50",
  438. .timings_type = VPBE_ENC_DV_TIMINGS,
  439. .dv_timings = V4L2_DV_BT_CEA_720X576P50,
  440. .interlaced = 0,
  441. .xres = 720,
  442. .yres = 576,
  443. .aspect = {1, 1},
  444. .fps = {50, 1},
  445. .left_margin = 0x8C,
  446. .upper_margin = 0x36,
  447. },
  448. {
  449. .name = "720p60",
  450. .timings_type = VPBE_ENC_DV_TIMINGS,
  451. .dv_timings = V4L2_DV_BT_CEA_1280X720P60,
  452. .interlaced = 0,
  453. .xres = 1280,
  454. .yres = 720,
  455. .aspect = {1, 1},
  456. .fps = {60, 1},
  457. .left_margin = 0x117,
  458. .right_margin = 70,
  459. .upper_margin = 38,
  460. .lower_margin = 3,
  461. .hsync_len = 80,
  462. .vsync_len = 5,
  463. },
  464. {
  465. .name = "1080i60",
  466. .timings_type = VPBE_ENC_DV_TIMINGS,
  467. .dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
  468. .interlaced = 1,
  469. .xres = 1920,
  470. .yres = 1080,
  471. .aspect = {1, 1},
  472. .fps = {30, 1},
  473. .left_margin = 0xc9,
  474. .right_margin = 80,
  475. .upper_margin = 30,
  476. .lower_margin = 3,
  477. .hsync_len = 88,
  478. .vsync_len = 5,
  479. },
  480. };
  481. #define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
  482. /*
  483. * The outputs available from VPBE + ecnoders. Keep the
  484. * the order same as that of encoders. First those from venc followed by that
  485. * from encoders. Index in the output refers to index on a particular
  486. * encoder.Driver uses this index to pass it to encoder when it supports more
  487. * than one output. Application uses index of the array to set an output.
  488. */
  489. static struct vpbe_output dm365evm_vpbe_outputs[] = {
  490. {
  491. .output = {
  492. .index = 0,
  493. .name = "Composite",
  494. .type = V4L2_OUTPUT_TYPE_ANALOG,
  495. .std = VENC_STD_ALL,
  496. .capabilities = V4L2_OUT_CAP_STD,
  497. },
  498. .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
  499. .default_mode = "ntsc",
  500. .num_modes = ARRAY_SIZE(dm365evm_enc_std_timing),
  501. .modes = dm365evm_enc_std_timing,
  502. .if_params = MEDIA_BUS_FMT_FIXED,
  503. },
  504. {
  505. .output = {
  506. .index = 1,
  507. .name = "Component",
  508. .type = V4L2_OUTPUT_TYPE_ANALOG,
  509. .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
  510. },
  511. .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
  512. .default_mode = "480p59_94",
  513. .num_modes = ARRAY_SIZE(dm365evm_enc_preset_timing),
  514. .modes = dm365evm_enc_preset_timing,
  515. .if_params = MEDIA_BUS_FMT_FIXED,
  516. },
  517. };
  518. /*
  519. * Amplifiers on the board
  520. */
  521. static struct ths7303_platform_data ths7303_pdata = {
  522. .ch_1 = 3,
  523. .ch_2 = 3,
  524. .ch_3 = 3,
  525. };
  526. static struct amp_config_info vpbe_amp = {
  527. .module_name = "ths7303",
  528. .is_i2c = 1,
  529. .board_info = {
  530. I2C_BOARD_INFO("ths7303", 0x2c),
  531. .platform_data = &ths7303_pdata,
  532. }
  533. };
  534. static struct vpbe_config dm365evm_display_cfg = {
  535. .module_name = "dm365-vpbe-display",
  536. .i2c_adapter_id = 1,
  537. .amp = &vpbe_amp,
  538. .osd = {
  539. .module_name = DM365_VPBE_OSD_SUBDEV_NAME,
  540. },
  541. .venc = {
  542. .module_name = DM365_VPBE_VENC_SUBDEV_NAME,
  543. },
  544. .num_outputs = ARRAY_SIZE(dm365evm_vpbe_outputs),
  545. .outputs = dm365evm_vpbe_outputs,
  546. };
  547. static void __init evm_init_i2c(void)
  548. {
  549. davinci_init_i2c(&i2c_pdata);
  550. i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
  551. }
  552. static inline int have_leds(void)
  553. {
  554. #ifdef CONFIG_LEDS_CLASS
  555. return 1;
  556. #else
  557. return 0;
  558. #endif
  559. }
  560. struct cpld_led {
  561. struct led_classdev cdev;
  562. u8 mask;
  563. };
  564. static const struct {
  565. const char *name;
  566. const char *trigger;
  567. } cpld_leds[] = {
  568. { "dm365evm::ds2", },
  569. { "dm365evm::ds3", },
  570. { "dm365evm::ds4", },
  571. { "dm365evm::ds5", },
  572. { "dm365evm::ds6", "nand-disk", },
  573. { "dm365evm::ds7", "mmc1", },
  574. { "dm365evm::ds8", "mmc0", },
  575. { "dm365evm::ds9", "heartbeat", },
  576. };
  577. static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
  578. {
  579. struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
  580. u8 reg = __raw_readb(cpld + CPLD_LEDS);
  581. if (b != LED_OFF)
  582. reg &= ~led->mask;
  583. else
  584. reg |= led->mask;
  585. __raw_writeb(reg, cpld + CPLD_LEDS);
  586. }
  587. static enum led_brightness cpld_led_get(struct led_classdev *cdev)
  588. {
  589. struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
  590. u8 reg = __raw_readb(cpld + CPLD_LEDS);
  591. return (reg & led->mask) ? LED_OFF : LED_FULL;
  592. }
  593. static int __init cpld_leds_init(void)
  594. {
  595. int i;
  596. if (!have_leds() || !cpld)
  597. return 0;
  598. /* setup LEDs */
  599. __raw_writeb(0xff, cpld + CPLD_LEDS);
  600. for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
  601. struct cpld_led *led;
  602. led = kzalloc(sizeof(*led), GFP_KERNEL);
  603. if (!led)
  604. break;
  605. led->cdev.name = cpld_leds[i].name;
  606. led->cdev.brightness_set = cpld_led_set;
  607. led->cdev.brightness_get = cpld_led_get;
  608. led->cdev.default_trigger = cpld_leds[i].trigger;
  609. led->mask = BIT(i);
  610. if (led_classdev_register(NULL, &led->cdev) < 0) {
  611. kfree(led);
  612. break;
  613. }
  614. }
  615. return 0;
  616. }
  617. /* run after subsys_initcall() for LEDs */
  618. fs_initcall(cpld_leds_init);
  619. static void __init evm_init_cpld(void)
  620. {
  621. u8 mux, resets;
  622. const char *label;
  623. struct clk *aemif_clk;
  624. int rc;
  625. /* Make sure we can configure the CPLD through CS1. Then
  626. * leave it on for later access to MMC and LED registers.
  627. */
  628. aemif_clk = clk_get(NULL, "aemif");
  629. if (IS_ERR(aemif_clk))
  630. return;
  631. clk_prepare_enable(aemif_clk);
  632. if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
  633. "cpld") == NULL)
  634. goto fail;
  635. cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
  636. if (!cpld) {
  637. release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
  638. SECTION_SIZE);
  639. fail:
  640. pr_err("ERROR: can't map CPLD\n");
  641. clk_disable_unprepare(aemif_clk);
  642. return;
  643. }
  644. /* External muxing for some signals */
  645. mux = 0;
  646. /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
  647. * NOTE: SW4 bus width setting must match!
  648. */
  649. if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
  650. /* external keypad mux */
  651. mux |= BIT(7);
  652. rc = platform_device_register(&davinci_aemif_device);
  653. if (rc)
  654. pr_warn("%s(): error registering the aemif device: %d\n",
  655. __func__, rc);
  656. } else {
  657. /* no OneNAND support yet */
  658. }
  659. /* Leave external chips in reset when unused. */
  660. resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
  661. /* Static video input config with SN74CBT16214 1-of-3 mux:
  662. * - port b1 == tvp7002 (mux lowbits == 1 or 6)
  663. * - port b2 == imager (mux lowbits == 2 or 7)
  664. * - port b3 == tvp5146 (mux lowbits == 5)
  665. *
  666. * Runtime switching could work too, with limitations.
  667. */
  668. if (have_imager()) {
  669. label = "HD imager";
  670. mux |= 2;
  671. /* externally mux MMC1/ENET/AIC33 to imager */
  672. mux |= BIT(6) | BIT(5) | BIT(3);
  673. } else {
  674. struct davinci_soc_info *soc_info = &davinci_soc_info;
  675. /* we can use MMC1 ... */
  676. dm365evm_mmc_configure();
  677. davinci_setup_mmc(1, &dm365evm_mmc_config);
  678. /* ... and ENET ... */
  679. dm365evm_emac_configure();
  680. soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
  681. resets &= ~BIT(3);
  682. /* ... and AIC33 */
  683. resets &= ~BIT(1);
  684. if (have_tvp7002()) {
  685. mux |= 1;
  686. resets &= ~BIT(2);
  687. label = "tvp7002 HD";
  688. } else {
  689. /* default to tvp5146 */
  690. mux |= 5;
  691. resets &= ~BIT(0);
  692. label = "tvp5146 SD";
  693. }
  694. }
  695. __raw_writeb(mux, cpld + CPLD_MUX);
  696. __raw_writeb(resets, cpld + CPLD_RESETS);
  697. pr_info("EVM: %s video input\n", label);
  698. /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
  699. }
  700. static void __init dm365_evm_map_io(void)
  701. {
  702. dm365_init();
  703. }
  704. static struct spi_eeprom at25640 = {
  705. .byte_len = SZ_64K / 8,
  706. .name = "at25640",
  707. .page_size = 32,
  708. .flags = EE_ADDR2,
  709. };
  710. static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
  711. {
  712. .modalias = "at25",
  713. .platform_data = &at25640,
  714. .max_speed_hz = 10 * 1000 * 1000,
  715. .bus_num = 0,
  716. .chip_select = 0,
  717. .mode = SPI_MODE_0,
  718. },
  719. };
  720. static __init void dm365_evm_init(void)
  721. {
  722. int ret;
  723. dm365_register_clocks();
  724. ret = dm365_gpio_register();
  725. if (ret)
  726. pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
  727. regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
  728. ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
  729. regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
  730. ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
  731. nvmem_add_cell_table(&davinci_nvmem_cell_table);
  732. nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1);
  733. evm_init_i2c();
  734. davinci_serial_init(dm365_serial_device);
  735. dm365evm_emac_configure();
  736. dm365evm_mmc_configure();
  737. davinci_setup_mmc(0, &dm365evm_mmc_config);
  738. dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
  739. /* maybe setup mmc1/etc ... _after_ mmc0 */
  740. evm_init_cpld();
  741. #ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC
  742. dm365_init_asp();
  743. #elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC)
  744. dm365_init_vc();
  745. #endif
  746. dm365_init_rtc();
  747. dm365_init_ks(&dm365evm_ks_data);
  748. dm365_init_spi0(BIT(0), dm365_evm_spi_info,
  749. ARRAY_SIZE(dm365_evm_spi_info));
  750. }
  751. MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
  752. .atag_offset = 0x100,
  753. .map_io = dm365_evm_map_io,
  754. .init_irq = dm365_init_irq,
  755. .init_time = dm365_init_time,
  756. .init_machine = dm365_evm_init,
  757. .init_late = davinci_init_late,
  758. .dma_zone_size = SZ_128M,
  759. MACHINE_END