xscale-cp0.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/kernel/xscale-cp0.c
  4. *
  5. * XScale DSP and iWMMXt coprocessor context switching and handling
  6. */
  7. #include <linux/types.h>
  8. #include <linux/kernel.h>
  9. #include <linux/signal.h>
  10. #include <linux/sched.h>
  11. #include <linux/init.h>
  12. #include <linux/io.h>
  13. #include <asm/thread_notify.h>
  14. #include <asm/cputype.h>
  15. asm(" .arch armv5te\n");
  16. static inline void dsp_save_state(u32 *state)
  17. {
  18. __asm__ __volatile__ (
  19. "mrrc p0, 0, %0, %1, c0\n"
  20. : "=r" (state[0]), "=r" (state[1]));
  21. }
  22. static inline void dsp_load_state(u32 *state)
  23. {
  24. __asm__ __volatile__ (
  25. "mcrr p0, 0, %0, %1, c0\n"
  26. : : "r" (state[0]), "r" (state[1]));
  27. }
  28. static int dsp_do(struct notifier_block *self, unsigned long cmd, void *t)
  29. {
  30. struct thread_info *thread = t;
  31. switch (cmd) {
  32. case THREAD_NOTIFY_FLUSH:
  33. thread->cpu_context.extra[0] = 0;
  34. thread->cpu_context.extra[1] = 0;
  35. break;
  36. case THREAD_NOTIFY_SWITCH:
  37. dsp_save_state(current_thread_info()->cpu_context.extra);
  38. dsp_load_state(thread->cpu_context.extra);
  39. break;
  40. }
  41. return NOTIFY_DONE;
  42. }
  43. static struct notifier_block dsp_notifier_block = {
  44. .notifier_call = dsp_do,
  45. };
  46. #ifdef CONFIG_IWMMXT
  47. static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
  48. {
  49. struct thread_info *thread = t;
  50. switch (cmd) {
  51. case THREAD_NOTIFY_FLUSH:
  52. /*
  53. * flush_thread() zeroes thread->fpstate, so no need
  54. * to do anything here.
  55. *
  56. * FALLTHROUGH: Ensure we don't try to overwrite our newly
  57. * initialised state information on the first fault.
  58. */
  59. case THREAD_NOTIFY_EXIT:
  60. iwmmxt_task_release(thread);
  61. break;
  62. case THREAD_NOTIFY_SWITCH:
  63. iwmmxt_task_switch(thread);
  64. break;
  65. }
  66. return NOTIFY_DONE;
  67. }
  68. static struct notifier_block iwmmxt_notifier_block = {
  69. .notifier_call = iwmmxt_do,
  70. };
  71. #endif
  72. static u32 __init xscale_cp_access_read(void)
  73. {
  74. u32 value;
  75. __asm__ __volatile__ (
  76. "mrc p15, 0, %0, c15, c1, 0\n\t"
  77. : "=r" (value));
  78. return value;
  79. }
  80. static void __init xscale_cp_access_write(u32 value)
  81. {
  82. u32 temp;
  83. __asm__ __volatile__ (
  84. "mcr p15, 0, %1, c15, c1, 0\n\t"
  85. "mrc p15, 0, %0, c15, c1, 0\n\t"
  86. "mov %0, %0\n\t"
  87. "sub pc, pc, #4\n\t"
  88. : "=r" (temp) : "r" (value));
  89. }
  90. /*
  91. * Detect whether we have a MAC coprocessor (40 bit register) or an
  92. * iWMMXt coprocessor (64 bit registers) by loading 00000100:00000000
  93. * into a coprocessor register and reading it back, and checking
  94. * whether the upper word survived intact.
  95. */
  96. static int __init cpu_has_iwmmxt(void)
  97. {
  98. u32 lo;
  99. u32 hi;
  100. /*
  101. * This sequence is interpreted by the DSP coprocessor as:
  102. * mar acc0, %2, %3
  103. * mra %0, %1, acc0
  104. *
  105. * And by the iWMMXt coprocessor as:
  106. * tmcrr wR0, %2, %3
  107. * tmrrc %0, %1, wR0
  108. */
  109. __asm__ __volatile__ (
  110. "mcrr p0, 0, %2, %3, c0\n"
  111. "mrrc p0, 0, %0, %1, c0\n"
  112. : "=r" (lo), "=r" (hi)
  113. : "r" (0), "r" (0x100));
  114. return !!hi;
  115. }
  116. /*
  117. * If we detect that the CPU has iWMMXt (and CONFIG_IWMMXT=y), we
  118. * disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
  119. * switch code handle iWMMXt context switching. If on the other
  120. * hand the CPU has a DSP coprocessor, we keep access to CP0 enabled
  121. * all the time, and save/restore acc0 on context switch in non-lazy
  122. * fashion.
  123. */
  124. static int __init xscale_cp0_init(void)
  125. {
  126. u32 cp_access;
  127. /* do not attempt to probe iwmmxt on non-xscale family CPUs */
  128. if (!cpu_is_xscale_family())
  129. return 0;
  130. cp_access = xscale_cp_access_read() & ~3;
  131. xscale_cp_access_write(cp_access | 1);
  132. if (cpu_has_iwmmxt()) {
  133. #ifndef CONFIG_IWMMXT
  134. pr_warn("CAUTION: XScale iWMMXt coprocessor detected, but kernel support is missing.\n");
  135. #else
  136. pr_info("XScale iWMMXt coprocessor detected.\n");
  137. elf_hwcap |= HWCAP_IWMMXT;
  138. thread_register_notifier(&iwmmxt_notifier_block);
  139. #endif
  140. } else {
  141. pr_info("XScale DSP coprocessor detected.\n");
  142. thread_register_notifier(&dsp_notifier_block);
  143. cp_access |= 1;
  144. }
  145. xscale_cp_access_write(cp_access);
  146. return 0;
  147. }
  148. late_initcall(xscale_cp0_init);