hyp-stub.S 6.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright (c) 2012 Linaro Limited.
  4. */
  5. #include <linux/init.h>
  6. #include <linux/irqchip/arm-gic-v3.h>
  7. #include <linux/linkage.h>
  8. #include <asm/assembler.h>
  9. #include <asm/virt.h>
  10. #ifndef ZIMAGE
  11. /*
  12. * For the kernel proper, we need to find out the CPU boot mode long after
  13. * boot, so we need to store it in a writable variable.
  14. *
  15. * This is not in .bss, because we set it sufficiently early that the boot-time
  16. * zeroing of .bss would clobber it.
  17. */
  18. .data
  19. .align 2
  20. ENTRY(__boot_cpu_mode)
  21. .long 0
  22. .text
  23. /*
  24. * Save the primary CPU boot mode. Requires 3 scratch registers.
  25. */
  26. .macro store_primary_cpu_mode reg1, reg2, reg3
  27. mrs \reg1, cpsr
  28. and \reg1, \reg1, #MODE_MASK
  29. adr \reg2, .L__boot_cpu_mode_offset
  30. ldr \reg3, [\reg2]
  31. str \reg1, [\reg2, \reg3]
  32. .endm
  33. /*
  34. * Compare the current mode with the one saved on the primary CPU.
  35. * If they don't match, record that fact. The Z bit indicates
  36. * if there's a match or not.
  37. * Requires 3 additionnal scratch registers.
  38. */
  39. .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
  40. adr \reg2, .L__boot_cpu_mode_offset
  41. ldr \reg3, [\reg2]
  42. ldr \reg1, [\reg2, \reg3]
  43. cmp \mode, \reg1 @ matches primary CPU boot mode?
  44. orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
  45. strne \reg1, [\reg2, \reg3] @ record what happened and give up
  46. .endm
  47. #else /* ZIMAGE */
  48. .macro store_primary_cpu_mode reg1:req, reg2:req, reg3:req
  49. .endm
  50. /*
  51. * The zImage loader only runs on one CPU, so we don't bother with mult-CPU
  52. * consistency checking:
  53. */
  54. .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
  55. cmp \mode, \mode
  56. .endm
  57. #endif /* ZIMAGE */
  58. /*
  59. * Hypervisor stub installation functions.
  60. *
  61. * These must be called with the MMU and D-cache off.
  62. * They are not ABI compliant and are only intended to be called from the kernel
  63. * entry points in head.S.
  64. */
  65. @ Call this from the primary CPU
  66. ENTRY(__hyp_stub_install)
  67. store_primary_cpu_mode r4, r5, r6
  68. ENDPROC(__hyp_stub_install)
  69. @ fall through...
  70. @ Secondary CPUs should call here
  71. ENTRY(__hyp_stub_install_secondary)
  72. mrs r4, cpsr
  73. and r4, r4, #MODE_MASK
  74. /*
  75. * If the secondary has booted with a different mode, give up
  76. * immediately.
  77. */
  78. compare_cpu_mode_with_primary r4, r5, r6, r7
  79. retne lr
  80. /*
  81. * Once we have given up on one CPU, we do not try to install the
  82. * stub hypervisor on the remaining ones: because the saved boot mode
  83. * is modified, it can't compare equal to the CPSR mode field any
  84. * more.
  85. *
  86. * Otherwise...
  87. */
  88. cmp r4, #HYP_MODE
  89. retne lr @ give up if the CPU is not in HYP mode
  90. /*
  91. * Configure HSCTLR to set correct exception endianness/instruction set
  92. * state etc.
  93. * Turn off all traps
  94. * Eventually, CPU-specific code might be needed -- assume not for now
  95. *
  96. * This code relies on the "eret" instruction to synchronize the
  97. * various coprocessor accesses. This is done when we switch to SVC
  98. * (see safe_svcmode_maskall).
  99. */
  100. @ Now install the hypervisor stub:
  101. W(adr) r7, __hyp_stub_vectors
  102. mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
  103. @ Disable all traps, so we don't get any nasty surprise
  104. mov r7, #0
  105. mcr p15, 4, r7, c1, c1, 0 @ HCR
  106. mcr p15, 4, r7, c1, c1, 2 @ HCPTR
  107. mcr p15, 4, r7, c1, c1, 3 @ HSTR
  108. THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
  109. ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE
  110. mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
  111. mrc p15, 4, r7, c1, c1, 1 @ HDCR
  112. and r7, #0x1f @ Preserve HPMN
  113. mcr p15, 4, r7, c1, c1, 1 @ HDCR
  114. @ Make sure NS-SVC is initialised appropriately
  115. mrc p15, 0, r7, c1, c0, 0 @ SCTLR
  116. orr r7, #(1 << 5) @ CP15 barriers enabled
  117. bic r7, #(3 << 7) @ Clear SED/ITD for v8 (RES0 for v7)
  118. bic r7, #(3 << 19) @ WXN and UWXN disabled
  119. mcr p15, 0, r7, c1, c0, 0 @ SCTLR
  120. mrc p15, 0, r7, c0, c0, 0 @ MIDR
  121. mcr p15, 4, r7, c0, c0, 0 @ VPIDR
  122. mrc p15, 0, r7, c0, c0, 5 @ MPIDR
  123. mcr p15, 4, r7, c0, c0, 5 @ VMPIDR
  124. #if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)
  125. @ make CNTP_* and CNTPCT accessible from PL1
  126. mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
  127. ubfx r7, r7, #16, #4
  128. teq r7, #0
  129. beq 1f
  130. mrc p15, 4, r7, c14, c1, 0 @ CNTHCTL
  131. orr r7, r7, #3 @ PL1PCEN | PL1PCTEN
  132. mcr p15, 4, r7, c14, c1, 0 @ CNTHCTL
  133. mov r7, #0
  134. mcrr p15, 4, r7, r7, c14 @ CNTVOFF
  135. @ Disable virtual timer in case it was counting
  136. mrc p15, 0, r7, c14, c3, 1 @ CNTV_CTL
  137. bic r7, #1 @ Clear ENABLE
  138. mcr p15, 0, r7, c14, c3, 1 @ CNTV_CTL
  139. 1:
  140. #endif
  141. #ifdef CONFIG_ARM_GIC_V3
  142. @ Check whether GICv3 system registers are available
  143. mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
  144. ubfx r7, r7, #28, #4
  145. teq r7, #0
  146. beq 2f
  147. @ Enable system register accesses
  148. mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
  149. orr r7, r7, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE)
  150. mcr p15, 4, r7, c12, c9, 5 @ ICC_HSRE
  151. isb
  152. @ SRE bit could be forced to 0 by firmware.
  153. @ Check whether it sticks before accessing any other sysreg
  154. mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
  155. tst r7, #ICC_SRE_EL2_SRE
  156. beq 2f
  157. mov r7, #0
  158. mcr p15, 4, r7, c12, c11, 0 @ ICH_HCR
  159. 2:
  160. #endif
  161. bx lr @ The boot CPU mode is left in r4.
  162. ENDPROC(__hyp_stub_install_secondary)
  163. __hyp_stub_do_trap:
  164. #ifdef ZIMAGE
  165. teq r0, #HVC_SET_VECTORS
  166. bne 1f
  167. /* Only the ZIMAGE stubs can change the HYP vectors */
  168. mcr p15, 4, r1, c12, c0, 0 @ set HVBAR
  169. b __hyp_stub_exit
  170. #endif
  171. 1: teq r0, #HVC_SOFT_RESTART
  172. bne 2f
  173. bx r1
  174. 2: ldr r0, =HVC_STUB_ERR
  175. __ERET
  176. __hyp_stub_exit:
  177. mov r0, #0
  178. __ERET
  179. ENDPROC(__hyp_stub_do_trap)
  180. /*
  181. * __hyp_set_vectors is only used when ZIMAGE must bounce between HYP
  182. * and SVC. For the kernel itself, the vectors are set once and for
  183. * all by the stubs.
  184. */
  185. ENTRY(__hyp_set_vectors)
  186. mov r1, r0
  187. mov r0, #HVC_SET_VECTORS
  188. __HVC(0)
  189. ret lr
  190. ENDPROC(__hyp_set_vectors)
  191. ENTRY(__hyp_soft_restart)
  192. mov r1, r0
  193. mov r0, #HVC_SOFT_RESTART
  194. __HVC(0)
  195. ret lr
  196. ENDPROC(__hyp_soft_restart)
  197. #ifndef ZIMAGE
  198. .align 2
  199. .L__boot_cpu_mode_offset:
  200. .long __boot_cpu_mode - .
  201. #endif
  202. .align 5
  203. ENTRY(__hyp_stub_vectors)
  204. __hyp_stub_reset: W(b) .
  205. __hyp_stub_und: W(b) .
  206. __hyp_stub_svc: W(b) .
  207. __hyp_stub_pabort: W(b) .
  208. __hyp_stub_dabort: W(b) .
  209. __hyp_stub_trap: W(b) __hyp_stub_do_trap
  210. __hyp_stub_irq: W(b) .
  211. __hyp_stub_fiq: W(b) .
  212. ENDPROC(__hyp_stub_vectors)