entry-armv.S 30 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/arch/arm/kernel/entry-armv.S
  4. *
  5. * Copyright (C) 1996,1997,1998 Russell King.
  6. * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
  7. * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
  8. *
  9. * Low-level vector interface routines
  10. *
  11. * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
  12. * that causes it to save wrong values... Be aware!
  13. */
  14. #include <linux/init.h>
  15. #include <asm/assembler.h>
  16. #include <asm/memory.h>
  17. #include <asm/glue-df.h>
  18. #include <asm/glue-pf.h>
  19. #include <asm/vfpmacros.h>
  20. #ifndef CONFIG_GENERIC_IRQ_MULTI_HANDLER
  21. #include <mach/entry-macro.S>
  22. #endif
  23. #include <asm/thread_notify.h>
  24. #include <asm/unwind.h>
  25. #include <asm/unistd.h>
  26. #include <asm/tls.h>
  27. #include <asm/system_info.h>
  28. #include <asm/uaccess-asm.h>
  29. #include "entry-header.S"
  30. #include <asm/entry-macro-multi.S>
  31. #include <asm/probes.h>
  32. /*
  33. * Interrupt handling.
  34. */
  35. .macro irq_handler
  36. #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
  37. ldr r1, =handle_arch_irq
  38. mov r0, sp
  39. badr lr, 9997f
  40. ldr pc, [r1]
  41. #else
  42. arch_irq_handler_default
  43. #endif
  44. 9997:
  45. .endm
  46. .macro pabt_helper
  47. @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
  48. #ifdef MULTI_PABORT
  49. ldr ip, .LCprocfns
  50. mov lr, pc
  51. ldr pc, [ip, #PROCESSOR_PABT_FUNC]
  52. #else
  53. bl CPU_PABORT_HANDLER
  54. #endif
  55. .endm
  56. .macro dabt_helper
  57. @
  58. @ Call the processor-specific abort handler:
  59. @
  60. @ r2 - pt_regs
  61. @ r4 - aborted context pc
  62. @ r5 - aborted context psr
  63. @
  64. @ The abort handler must return the aborted address in r0, and
  65. @ the fault status register in r1. r9 must be preserved.
  66. @
  67. #ifdef MULTI_DABORT
  68. ldr ip, .LCprocfns
  69. mov lr, pc
  70. ldr pc, [ip, #PROCESSOR_DABT_FUNC]
  71. #else
  72. bl CPU_DABORT_HANDLER
  73. #endif
  74. .endm
  75. .section .entry.text,"ax",%progbits
  76. /*
  77. * Invalid mode handlers
  78. */
  79. .macro inv_entry, reason
  80. sub sp, sp, #PT_REGS_SIZE
  81. ARM( stmib sp, {r1 - lr} )
  82. THUMB( stmia sp, {r0 - r12} )
  83. THUMB( str sp, [sp, #S_SP] )
  84. THUMB( str lr, [sp, #S_LR] )
  85. mov r1, #\reason
  86. .endm
  87. __pabt_invalid:
  88. inv_entry BAD_PREFETCH
  89. b common_invalid
  90. ENDPROC(__pabt_invalid)
  91. __dabt_invalid:
  92. inv_entry BAD_DATA
  93. b common_invalid
  94. ENDPROC(__dabt_invalid)
  95. __irq_invalid:
  96. inv_entry BAD_IRQ
  97. b common_invalid
  98. ENDPROC(__irq_invalid)
  99. __und_invalid:
  100. inv_entry BAD_UNDEFINSTR
  101. @
  102. @ XXX fall through to common_invalid
  103. @
  104. @
  105. @ common_invalid - generic code for failed exception (re-entrant version of handlers)
  106. @
  107. common_invalid:
  108. zero_fp
  109. ldmia r0, {r4 - r6}
  110. add r0, sp, #S_PC @ here for interlock avoidance
  111. mov r7, #-1 @ "" "" "" ""
  112. str r4, [sp] @ save preserved r0
  113. stmia r0, {r5 - r7} @ lr_<exception>,
  114. @ cpsr_<exception>, "old_r0"
  115. mov r0, sp
  116. b bad_mode
  117. ENDPROC(__und_invalid)
  118. /*
  119. * SVC mode handlers
  120. */
  121. #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
  122. #define SPFIX(code...) code
  123. #else
  124. #define SPFIX(code...)
  125. #endif
  126. .macro svc_entry, stack_hole=0, trace=1, uaccess=1
  127. UNWIND(.fnstart )
  128. UNWIND(.save {r0 - pc} )
  129. sub sp, sp, #(SVC_REGS_SIZE + \stack_hole - 4)
  130. #ifdef CONFIG_THUMB2_KERNEL
  131. SPFIX( str r0, [sp] ) @ temporarily saved
  132. SPFIX( mov r0, sp )
  133. SPFIX( tst r0, #4 ) @ test original stack alignment
  134. SPFIX( ldr r0, [sp] ) @ restored
  135. #else
  136. SPFIX( tst sp, #4 )
  137. #endif
  138. SPFIX( subeq sp, sp, #4 )
  139. stmia sp, {r1 - r12}
  140. ldmia r0, {r3 - r5}
  141. add r7, sp, #S_SP - 4 @ here for interlock avoidance
  142. mov r6, #-1 @ "" "" "" ""
  143. add r2, sp, #(SVC_REGS_SIZE + \stack_hole - 4)
  144. SPFIX( addeq r2, r2, #4 )
  145. str r3, [sp, #-4]! @ save the "real" r0 copied
  146. @ from the exception stack
  147. mov r3, lr
  148. @
  149. @ We are now ready to fill in the remaining blanks on the stack:
  150. @
  151. @ r2 - sp_svc
  152. @ r3 - lr_svc
  153. @ r4 - lr_<exception>, already fixed up for correct return/restart
  154. @ r5 - spsr_<exception>
  155. @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
  156. @
  157. stmia r7, {r2 - r6}
  158. get_thread_info tsk
  159. uaccess_entry tsk, r0, r1, r2, \uaccess
  160. .if \trace
  161. #ifdef CONFIG_TRACE_IRQFLAGS
  162. bl trace_hardirqs_off
  163. #endif
  164. .endif
  165. .endm
  166. .align 5
  167. __dabt_svc:
  168. svc_entry uaccess=0
  169. mov r2, sp
  170. dabt_helper
  171. THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR
  172. svc_exit r5 @ return from exception
  173. UNWIND(.fnend )
  174. ENDPROC(__dabt_svc)
  175. .align 5
  176. __irq_svc:
  177. svc_entry
  178. irq_handler
  179. #ifdef CONFIG_PREEMPTION
  180. ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
  181. ldr r0, [tsk, #TI_FLAGS] @ get flags
  182. teq r8, #0 @ if preempt count != 0
  183. movne r0, #0 @ force flags to 0
  184. tst r0, #_TIF_NEED_RESCHED
  185. blne svc_preempt
  186. #endif
  187. svc_exit r5, irq = 1 @ return from exception
  188. UNWIND(.fnend )
  189. ENDPROC(__irq_svc)
  190. .ltorg
  191. #ifdef CONFIG_PREEMPTION
  192. svc_preempt:
  193. mov r8, lr
  194. 1: bl preempt_schedule_irq @ irq en/disable is done inside
  195. ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
  196. tst r0, #_TIF_NEED_RESCHED
  197. reteq r8 @ go again
  198. b 1b
  199. #endif
  200. __und_fault:
  201. @ Correct the PC such that it is pointing at the instruction
  202. @ which caused the fault. If the faulting instruction was ARM
  203. @ the PC will be pointing at the next instruction, and have to
  204. @ subtract 4. Otherwise, it is Thumb, and the PC will be
  205. @ pointing at the second half of the Thumb instruction. We
  206. @ have to subtract 2.
  207. ldr r2, [r0, #S_PC]
  208. sub r2, r2, r1
  209. str r2, [r0, #S_PC]
  210. b do_undefinstr
  211. ENDPROC(__und_fault)
  212. .align 5
  213. __und_svc:
  214. #ifdef CONFIG_KPROBES
  215. @ If a kprobe is about to simulate a "stmdb sp..." instruction,
  216. @ it obviously needs free stack space which then will belong to
  217. @ the saved context.
  218. svc_entry MAX_STACK_SIZE
  219. #else
  220. svc_entry
  221. #endif
  222. mov r1, #4 @ PC correction to apply
  223. THUMB( tst r5, #PSR_T_BIT ) @ exception taken in Thumb mode?
  224. THUMB( movne r1, #2 ) @ if so, fix up PC correction
  225. mov r0, sp @ struct pt_regs *regs
  226. bl __und_fault
  227. __und_svc_finish:
  228. get_thread_info tsk
  229. ldr r5, [sp, #S_PSR] @ Get SVC cpsr
  230. svc_exit r5 @ return from exception
  231. UNWIND(.fnend )
  232. ENDPROC(__und_svc)
  233. .align 5
  234. __pabt_svc:
  235. svc_entry
  236. mov r2, sp @ regs
  237. pabt_helper
  238. svc_exit r5 @ return from exception
  239. UNWIND(.fnend )
  240. ENDPROC(__pabt_svc)
  241. .align 5
  242. __fiq_svc:
  243. svc_entry trace=0
  244. mov r0, sp @ struct pt_regs *regs
  245. bl handle_fiq_as_nmi
  246. svc_exit_via_fiq
  247. UNWIND(.fnend )
  248. ENDPROC(__fiq_svc)
  249. .align 5
  250. .LCcralign:
  251. .word cr_alignment
  252. #ifdef MULTI_DABORT
  253. .LCprocfns:
  254. .word processor
  255. #endif
  256. .LCfp:
  257. .word fp_enter
  258. /*
  259. * Abort mode handlers
  260. */
  261. @
  262. @ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode
  263. @ and reuses the same macros. However in abort mode we must also
  264. @ save/restore lr_abt and spsr_abt to make nested aborts safe.
  265. @
  266. .align 5
  267. __fiq_abt:
  268. svc_entry trace=0
  269. ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
  270. THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
  271. THUMB( msr cpsr_c, r0 )
  272. mov r1, lr @ Save lr_abt
  273. mrs r2, spsr @ Save spsr_abt, abort is now safe
  274. ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
  275. THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
  276. THUMB( msr cpsr_c, r0 )
  277. stmfd sp!, {r1 - r2}
  278. add r0, sp, #8 @ struct pt_regs *regs
  279. bl handle_fiq_as_nmi
  280. ldmfd sp!, {r1 - r2}
  281. ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
  282. THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
  283. THUMB( msr cpsr_c, r0 )
  284. mov lr, r1 @ Restore lr_abt, abort is unsafe
  285. msr spsr_cxsf, r2 @ Restore spsr_abt
  286. ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
  287. THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
  288. THUMB( msr cpsr_c, r0 )
  289. svc_exit_via_fiq
  290. UNWIND(.fnend )
  291. ENDPROC(__fiq_abt)
  292. /*
  293. * User mode handlers
  294. *
  295. * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE
  296. */
  297. #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (PT_REGS_SIZE & 7)
  298. #error "sizeof(struct pt_regs) must be a multiple of 8"
  299. #endif
  300. .macro usr_entry, trace=1, uaccess=1
  301. UNWIND(.fnstart )
  302. UNWIND(.cantunwind ) @ don't unwind the user space
  303. sub sp, sp, #PT_REGS_SIZE
  304. ARM( stmib sp, {r1 - r12} )
  305. THUMB( stmia sp, {r0 - r12} )
  306. ATRAP( mrc p15, 0, r7, c1, c0, 0)
  307. ATRAP( ldr r8, .LCcralign)
  308. ldmia r0, {r3 - r5}
  309. add r0, sp, #S_PC @ here for interlock avoidance
  310. mov r6, #-1 @ "" "" "" ""
  311. str r3, [sp] @ save the "real" r0 copied
  312. @ from the exception stack
  313. ATRAP( ldr r8, [r8, #0])
  314. @
  315. @ We are now ready to fill in the remaining blanks on the stack:
  316. @
  317. @ r4 - lr_<exception>, already fixed up for correct return/restart
  318. @ r5 - spsr_<exception>
  319. @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
  320. @
  321. @ Also, separately save sp_usr and lr_usr
  322. @
  323. stmia r0, {r4 - r6}
  324. ARM( stmdb r0, {sp, lr}^ )
  325. THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
  326. .if \uaccess
  327. uaccess_disable ip
  328. .endif
  329. @ Enable the alignment trap while in kernel mode
  330. ATRAP( teq r8, r7)
  331. ATRAP( mcrne p15, 0, r8, c1, c0, 0)
  332. @
  333. @ Clear FP to mark the first stack frame
  334. @
  335. zero_fp
  336. .if \trace
  337. #ifdef CONFIG_TRACE_IRQFLAGS
  338. bl trace_hardirqs_off
  339. #endif
  340. ct_user_exit save = 0
  341. .endif
  342. .endm
  343. .macro kuser_cmpxchg_check
  344. #if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS)
  345. #ifndef CONFIG_MMU
  346. #warning "NPTL on non MMU needs fixing"
  347. #else
  348. @ Make sure our user space atomic helper is restarted
  349. @ if it was interrupted in a critical region. Here we
  350. @ perform a quick test inline since it should be false
  351. @ 99.9999% of the time. The rest is done out of line.
  352. cmp r4, #TASK_SIZE
  353. blhs kuser_cmpxchg64_fixup
  354. #endif
  355. #endif
  356. .endm
  357. .align 5
  358. __dabt_usr:
  359. usr_entry uaccess=0
  360. kuser_cmpxchg_check
  361. mov r2, sp
  362. dabt_helper
  363. b ret_from_exception
  364. UNWIND(.fnend )
  365. ENDPROC(__dabt_usr)
  366. .align 5
  367. __irq_usr:
  368. usr_entry
  369. kuser_cmpxchg_check
  370. irq_handler
  371. get_thread_info tsk
  372. mov why, #0
  373. b ret_to_user_from_irq
  374. UNWIND(.fnend )
  375. ENDPROC(__irq_usr)
  376. .ltorg
  377. .align 5
  378. __und_usr:
  379. usr_entry uaccess=0
  380. mov r2, r4
  381. mov r3, r5
  382. @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
  383. @ faulting instruction depending on Thumb mode.
  384. @ r3 = regs->ARM_cpsr
  385. @
  386. @ The emulation code returns using r9 if it has emulated the
  387. @ instruction, or the more conventional lr if we are to treat
  388. @ this as a real undefined instruction
  389. @
  390. badr r9, ret_from_exception
  391. @ IRQs must be enabled before attempting to read the instruction from
  392. @ user space since that could cause a page/translation fault if the
  393. @ page table was modified by another CPU.
  394. enable_irq
  395. tst r3, #PSR_T_BIT @ Thumb mode?
  396. bne __und_usr_thumb
  397. sub r4, r2, #4 @ ARM instr at LR - 4
  398. 1: ldrt r0, [r4]
  399. ARM_BE8(rev r0, r0) @ little endian instruction
  400. uaccess_disable ip
  401. @ r0 = 32-bit ARM instruction which caused the exception
  402. @ r2 = PC value for the following instruction (:= regs->ARM_pc)
  403. @ r4 = PC value for the faulting instruction
  404. @ lr = 32-bit undefined instruction function
  405. badr lr, __und_usr_fault_32
  406. b call_fpe
  407. __und_usr_thumb:
  408. @ Thumb instruction
  409. sub r4, r2, #2 @ First half of thumb instr at LR - 2
  410. #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
  411. /*
  412. * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
  413. * can never be supported in a single kernel, this code is not applicable at
  414. * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
  415. * made about .arch directives.
  416. */
  417. #if __LINUX_ARM_ARCH__ < 7
  418. /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
  419. #define NEED_CPU_ARCHITECTURE
  420. ldr r5, .LCcpu_architecture
  421. ldr r5, [r5]
  422. cmp r5, #CPU_ARCH_ARMv7
  423. blo __und_usr_fault_16 @ 16bit undefined instruction
  424. /*
  425. * The following code won't get run unless the running CPU really is v7, so
  426. * coding round the lack of ldrht on older arches is pointless. Temporarily
  427. * override the assembler target arch with the minimum required instead:
  428. */
  429. .arch armv6t2
  430. #endif
  431. 2: ldrht r5, [r4]
  432. ARM_BE8(rev16 r5, r5) @ little endian instruction
  433. cmp r5, #0xe800 @ 32bit instruction if xx != 0
  434. blo __und_usr_fault_16_pan @ 16bit undefined instruction
  435. 3: ldrht r0, [r2]
  436. ARM_BE8(rev16 r0, r0) @ little endian instruction
  437. uaccess_disable ip
  438. add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
  439. str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
  440. orr r0, r0, r5, lsl #16
  441. badr lr, __und_usr_fault_32
  442. @ r0 = the two 16-bit Thumb instructions which caused the exception
  443. @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
  444. @ r4 = PC value for the first 16-bit Thumb instruction
  445. @ lr = 32bit undefined instruction function
  446. #if __LINUX_ARM_ARCH__ < 7
  447. /* If the target arch was overridden, change it back: */
  448. #ifdef CONFIG_CPU_32v6K
  449. .arch armv6k
  450. #else
  451. .arch armv6
  452. #endif
  453. #endif /* __LINUX_ARM_ARCH__ < 7 */
  454. #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
  455. b __und_usr_fault_16
  456. #endif
  457. UNWIND(.fnend)
  458. ENDPROC(__und_usr)
  459. /*
  460. * The out of line fixup for the ldrt instructions above.
  461. */
  462. .pushsection .text.fixup, "ax"
  463. .align 2
  464. 4: str r4, [sp, #S_PC] @ retry current instruction
  465. ret r9
  466. .popsection
  467. .pushsection __ex_table,"a"
  468. .long 1b, 4b
  469. #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
  470. .long 2b, 4b
  471. .long 3b, 4b
  472. #endif
  473. .popsection
  474. /*
  475. * Check whether the instruction is a co-processor instruction.
  476. * If yes, we need to call the relevant co-processor handler.
  477. *
  478. * Note that we don't do a full check here for the co-processor
  479. * instructions; all instructions with bit 27 set are well
  480. * defined. The only instructions that should fault are the
  481. * co-processor instructions. However, we have to watch out
  482. * for the ARM6/ARM7 SWI bug.
  483. *
  484. * NEON is a special case that has to be handled here. Not all
  485. * NEON instructions are co-processor instructions, so we have
  486. * to make a special case of checking for them. Plus, there's
  487. * five groups of them, so we have a table of mask/opcode pairs
  488. * to check against, and if any match then we branch off into the
  489. * NEON handler code.
  490. *
  491. * Emulators may wish to make use of the following registers:
  492. * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
  493. * r2 = PC value to resume execution after successful emulation
  494. * r9 = normal "successful" return address
  495. * r10 = this threads thread_info structure
  496. * lr = unrecognised instruction return address
  497. * IRQs enabled, FIQs enabled.
  498. */
  499. @
  500. @ Fall-through from Thumb-2 __und_usr
  501. @
  502. #ifdef CONFIG_NEON
  503. get_thread_info r10 @ get current thread
  504. adr r6, .LCneon_thumb_opcodes
  505. b 2f
  506. #endif
  507. call_fpe:
  508. get_thread_info r10 @ get current thread
  509. #ifdef CONFIG_NEON
  510. adr r6, .LCneon_arm_opcodes
  511. 2: ldr r5, [r6], #4 @ mask value
  512. ldr r7, [r6], #4 @ opcode bits matching in mask
  513. cmp r5, #0 @ end mask?
  514. beq 1f
  515. and r8, r0, r5
  516. cmp r8, r7 @ NEON instruction?
  517. bne 2b
  518. mov r7, #1
  519. strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
  520. strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
  521. b do_vfp @ let VFP handler handle this
  522. 1:
  523. #endif
  524. tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
  525. tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
  526. reteq lr
  527. and r8, r0, #0x00000f00 @ mask out CP number
  528. mov r7, #1
  529. add r6, r10, r8, lsr #8 @ add used_cp[] array offset first
  530. strb r7, [r6, #TI_USED_CP] @ set appropriate used_cp[]
  531. #ifdef CONFIG_IWMMXT
  532. @ Test if we need to give access to iWMMXt coprocessors
  533. ldr r5, [r10, #TI_FLAGS]
  534. rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
  535. movscs r7, r5, lsr #(TIF_USING_IWMMXT + 1)
  536. bcs iwmmxt_task_enable
  537. #endif
  538. ARM( add pc, pc, r8, lsr #6 )
  539. THUMB( lsr r8, r8, #6 )
  540. THUMB( add pc, r8 )
  541. nop
  542. ret.w lr @ CP#0
  543. W(b) do_fpe @ CP#1 (FPE)
  544. W(b) do_fpe @ CP#2 (FPE)
  545. ret.w lr @ CP#3
  546. #ifdef CONFIG_CRUNCH
  547. b crunch_task_enable @ CP#4 (MaverickCrunch)
  548. b crunch_task_enable @ CP#5 (MaverickCrunch)
  549. b crunch_task_enable @ CP#6 (MaverickCrunch)
  550. #else
  551. ret.w lr @ CP#4
  552. ret.w lr @ CP#5
  553. ret.w lr @ CP#6
  554. #endif
  555. ret.w lr @ CP#7
  556. ret.w lr @ CP#8
  557. ret.w lr @ CP#9
  558. #ifdef CONFIG_VFP
  559. W(b) do_vfp @ CP#10 (VFP)
  560. W(b) do_vfp @ CP#11 (VFP)
  561. #else
  562. ret.w lr @ CP#10 (VFP)
  563. ret.w lr @ CP#11 (VFP)
  564. #endif
  565. ret.w lr @ CP#12
  566. ret.w lr @ CP#13
  567. ret.w lr @ CP#14 (Debug)
  568. ret.w lr @ CP#15 (Control)
  569. #ifdef NEED_CPU_ARCHITECTURE
  570. .align 2
  571. .LCcpu_architecture:
  572. .word __cpu_architecture
  573. #endif
  574. #ifdef CONFIG_NEON
  575. .align 6
  576. .LCneon_arm_opcodes:
  577. .word 0xfe000000 @ mask
  578. .word 0xf2000000 @ opcode
  579. .word 0xff100000 @ mask
  580. .word 0xf4000000 @ opcode
  581. .word 0x00000000 @ mask
  582. .word 0x00000000 @ opcode
  583. .LCneon_thumb_opcodes:
  584. .word 0xef000000 @ mask
  585. .word 0xef000000 @ opcode
  586. .word 0xff100000 @ mask
  587. .word 0xf9000000 @ opcode
  588. .word 0x00000000 @ mask
  589. .word 0x00000000 @ opcode
  590. #endif
  591. do_fpe:
  592. ldr r4, .LCfp
  593. add r10, r10, #TI_FPSTATE @ r10 = workspace
  594. ldr pc, [r4] @ Call FP module USR entry point
  595. /*
  596. * The FP module is called with these registers set:
  597. * r0 = instruction
  598. * r2 = PC+4
  599. * r9 = normal "successful" return address
  600. * r10 = FP workspace
  601. * lr = unrecognised FP instruction return address
  602. */
  603. .pushsection .data
  604. .align 2
  605. ENTRY(fp_enter)
  606. .word no_fp
  607. .popsection
  608. ENTRY(no_fp)
  609. ret lr
  610. ENDPROC(no_fp)
  611. __und_usr_fault_32:
  612. mov r1, #4
  613. b 1f
  614. __und_usr_fault_16_pan:
  615. uaccess_disable ip
  616. __und_usr_fault_16:
  617. mov r1, #2
  618. 1: mov r0, sp
  619. badr lr, ret_from_exception
  620. b __und_fault
  621. ENDPROC(__und_usr_fault_32)
  622. ENDPROC(__und_usr_fault_16)
  623. .align 5
  624. __pabt_usr:
  625. usr_entry
  626. mov r2, sp @ regs
  627. pabt_helper
  628. UNWIND(.fnend )
  629. /* fall through */
  630. /*
  631. * This is the return code to user mode for abort handlers
  632. */
  633. ENTRY(ret_from_exception)
  634. UNWIND(.fnstart )
  635. UNWIND(.cantunwind )
  636. get_thread_info tsk
  637. mov why, #0
  638. b ret_to_user
  639. UNWIND(.fnend )
  640. ENDPROC(__pabt_usr)
  641. ENDPROC(ret_from_exception)
  642. .align 5
  643. __fiq_usr:
  644. usr_entry trace=0
  645. kuser_cmpxchg_check
  646. mov r0, sp @ struct pt_regs *regs
  647. bl handle_fiq_as_nmi
  648. get_thread_info tsk
  649. restore_user_regs fast = 0, offset = 0
  650. UNWIND(.fnend )
  651. ENDPROC(__fiq_usr)
  652. /*
  653. * Register switch for ARMv3 and ARMv4 processors
  654. * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
  655. * previous and next are guaranteed not to be the same.
  656. */
  657. ENTRY(__switch_to)
  658. UNWIND(.fnstart )
  659. UNWIND(.cantunwind )
  660. add ip, r1, #TI_CPU_SAVE
  661. ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
  662. THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
  663. THUMB( str sp, [ip], #4 )
  664. THUMB( str lr, [ip], #4 )
  665. ldr r4, [r2, #TI_TP_VALUE]
  666. ldr r5, [r2, #TI_TP_VALUE + 4]
  667. #ifdef CONFIG_CPU_USE_DOMAINS
  668. mrc p15, 0, r6, c3, c0, 0 @ Get domain register
  669. str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register
  670. ldr r6, [r2, #TI_CPU_DOMAIN]
  671. #endif
  672. switch_tls r1, r4, r5, r3, r7
  673. #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP)
  674. ldr r7, [r2, #TI_TASK]
  675. ldr r8, =__stack_chk_guard
  676. .if (TSK_STACK_CANARY > IMM12_MASK)
  677. add r7, r7, #TSK_STACK_CANARY & ~IMM12_MASK
  678. .endif
  679. ldr r7, [r7, #TSK_STACK_CANARY & IMM12_MASK]
  680. #endif
  681. #ifdef CONFIG_CPU_USE_DOMAINS
  682. mcr p15, 0, r6, c3, c0, 0 @ Set domain register
  683. #endif
  684. mov r5, r0
  685. add r4, r2, #TI_CPU_SAVE
  686. ldr r0, =thread_notify_head
  687. mov r1, #THREAD_NOTIFY_SWITCH
  688. bl atomic_notifier_call_chain
  689. #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP)
  690. str r7, [r8]
  691. #endif
  692. THUMB( mov ip, r4 )
  693. mov r0, r5
  694. ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
  695. THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
  696. THUMB( ldr sp, [ip], #4 )
  697. THUMB( ldr pc, [ip] )
  698. UNWIND(.fnend )
  699. ENDPROC(__switch_to)
  700. __INIT
  701. /*
  702. * User helpers.
  703. *
  704. * Each segment is 32-byte aligned and will be moved to the top of the high
  705. * vector page. New segments (if ever needed) must be added in front of
  706. * existing ones. This mechanism should be used only for things that are
  707. * really small and justified, and not be abused freely.
  708. *
  709. * See Documentation/arm/kernel_user_helpers.rst for formal definitions.
  710. */
  711. THUMB( .arm )
  712. .macro usr_ret, reg
  713. #ifdef CONFIG_ARM_THUMB
  714. bx \reg
  715. #else
  716. ret \reg
  717. #endif
  718. .endm
  719. .macro kuser_pad, sym, size
  720. .if (. - \sym) & 3
  721. .rept 4 - (. - \sym) & 3
  722. .byte 0
  723. .endr
  724. .endif
  725. .rept (\size - (. - \sym)) / 4
  726. .word 0xe7fddef1
  727. .endr
  728. .endm
  729. #ifdef CONFIG_KUSER_HELPERS
  730. .align 5
  731. .globl __kuser_helper_start
  732. __kuser_helper_start:
  733. /*
  734. * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
  735. * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
  736. */
  737. __kuser_cmpxchg64: @ 0xffff0f60
  738. #if defined(CONFIG_CPU_32v6K)
  739. stmfd sp!, {r4, r5, r6, r7}
  740. ldrd r4, r5, [r0] @ load old val
  741. ldrd r6, r7, [r1] @ load new val
  742. smp_dmb arm
  743. 1: ldrexd r0, r1, [r2] @ load current val
  744. eors r3, r0, r4 @ compare with oldval (1)
  745. eorseq r3, r1, r5 @ compare with oldval (2)
  746. strexdeq r3, r6, r7, [r2] @ store newval if eq
  747. teqeq r3, #1 @ success?
  748. beq 1b @ if no then retry
  749. smp_dmb arm
  750. rsbs r0, r3, #0 @ set returned val and C flag
  751. ldmfd sp!, {r4, r5, r6, r7}
  752. usr_ret lr
  753. #elif !defined(CONFIG_SMP)
  754. #ifdef CONFIG_MMU
  755. /*
  756. * The only thing that can break atomicity in this cmpxchg64
  757. * implementation is either an IRQ or a data abort exception
  758. * causing another process/thread to be scheduled in the middle of
  759. * the critical sequence. The same strategy as for cmpxchg is used.
  760. */
  761. stmfd sp!, {r4, r5, r6, lr}
  762. ldmia r0, {r4, r5} @ load old val
  763. ldmia r1, {r6, lr} @ load new val
  764. 1: ldmia r2, {r0, r1} @ load current val
  765. eors r3, r0, r4 @ compare with oldval (1)
  766. eorseq r3, r1, r5 @ compare with oldval (2)
  767. 2: stmiaeq r2, {r6, lr} @ store newval if eq
  768. rsbs r0, r3, #0 @ set return val and C flag
  769. ldmfd sp!, {r4, r5, r6, pc}
  770. .text
  771. kuser_cmpxchg64_fixup:
  772. @ Called from kuser_cmpxchg_fixup.
  773. @ r4 = address of interrupted insn (must be preserved).
  774. @ sp = saved regs. r7 and r8 are clobbered.
  775. @ 1b = first critical insn, 2b = last critical insn.
  776. @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
  777. mov r7, #0xffff0fff
  778. sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
  779. subs r8, r4, r7
  780. rsbscs r8, r8, #(2b - 1b)
  781. strcs r7, [sp, #S_PC]
  782. #if __LINUX_ARM_ARCH__ < 6
  783. bcc kuser_cmpxchg32_fixup
  784. #endif
  785. ret lr
  786. .previous
  787. #else
  788. #warning "NPTL on non MMU needs fixing"
  789. mov r0, #-1
  790. adds r0, r0, #0
  791. usr_ret lr
  792. #endif
  793. #else
  794. #error "incoherent kernel configuration"
  795. #endif
  796. kuser_pad __kuser_cmpxchg64, 64
  797. __kuser_memory_barrier: @ 0xffff0fa0
  798. smp_dmb arm
  799. usr_ret lr
  800. kuser_pad __kuser_memory_barrier, 32
  801. __kuser_cmpxchg: @ 0xffff0fc0
  802. #if __LINUX_ARM_ARCH__ < 6
  803. #ifdef CONFIG_MMU
  804. /*
  805. * The only thing that can break atomicity in this cmpxchg
  806. * implementation is either an IRQ or a data abort exception
  807. * causing another process/thread to be scheduled in the middle
  808. * of the critical sequence. To prevent this, code is added to
  809. * the IRQ and data abort exception handlers to set the pc back
  810. * to the beginning of the critical section if it is found to be
  811. * within that critical section (see kuser_cmpxchg_fixup).
  812. */
  813. 1: ldr r3, [r2] @ load current val
  814. subs r3, r3, r0 @ compare with oldval
  815. 2: streq r1, [r2] @ store newval if eq
  816. rsbs r0, r3, #0 @ set return val and C flag
  817. usr_ret lr
  818. .text
  819. kuser_cmpxchg32_fixup:
  820. @ Called from kuser_cmpxchg_check macro.
  821. @ r4 = address of interrupted insn (must be preserved).
  822. @ sp = saved regs. r7 and r8 are clobbered.
  823. @ 1b = first critical insn, 2b = last critical insn.
  824. @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
  825. mov r7, #0xffff0fff
  826. sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
  827. subs r8, r4, r7
  828. rsbscs r8, r8, #(2b - 1b)
  829. strcs r7, [sp, #S_PC]
  830. ret lr
  831. .previous
  832. #else
  833. #warning "NPTL on non MMU needs fixing"
  834. mov r0, #-1
  835. adds r0, r0, #0
  836. usr_ret lr
  837. #endif
  838. #else
  839. smp_dmb arm
  840. 1: ldrex r3, [r2]
  841. subs r3, r3, r0
  842. strexeq r3, r1, [r2]
  843. teqeq r3, #1
  844. beq 1b
  845. rsbs r0, r3, #0
  846. /* beware -- each __kuser slot must be 8 instructions max */
  847. ALT_SMP(b __kuser_memory_barrier)
  848. ALT_UP(usr_ret lr)
  849. #endif
  850. kuser_pad __kuser_cmpxchg, 32
  851. __kuser_get_tls: @ 0xffff0fe0
  852. ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
  853. usr_ret lr
  854. mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
  855. kuser_pad __kuser_get_tls, 16
  856. .rep 3
  857. .word 0 @ 0xffff0ff0 software TLS value, then
  858. .endr @ pad up to __kuser_helper_version
  859. __kuser_helper_version: @ 0xffff0ffc
  860. .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
  861. .globl __kuser_helper_end
  862. __kuser_helper_end:
  863. #endif
  864. THUMB( .thumb )
  865. /*
  866. * Vector stubs.
  867. *
  868. * This code is copied to 0xffff1000 so we can use branches in the
  869. * vectors, rather than ldr's. Note that this code must not exceed
  870. * a page size.
  871. *
  872. * Common stub entry macro:
  873. * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
  874. *
  875. * SP points to a minimal amount of processor-private memory, the address
  876. * of which is copied into r0 for the mode specific abort handler.
  877. */
  878. .macro vector_stub, name, mode, correction=0
  879. .align 5
  880. vector_\name:
  881. .if \correction
  882. sub lr, lr, #\correction
  883. .endif
  884. @ Save r0, lr_<exception> (parent PC)
  885. stmia sp, {r0, lr} @ save r0, lr
  886. @ Save spsr_<exception> (parent CPSR)
  887. 2: mrs lr, spsr
  888. str lr, [sp, #8] @ save spsr
  889. @
  890. @ Prepare for SVC32 mode. IRQs remain disabled.
  891. @
  892. mrs r0, cpsr
  893. eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
  894. msr spsr_cxsf, r0
  895. @
  896. @ the branch table must immediately follow this code
  897. @
  898. and lr, lr, #0x0f
  899. THUMB( adr r0, 1f )
  900. THUMB( ldr lr, [r0, lr, lsl #2] )
  901. mov r0, sp
  902. ARM( ldr lr, [pc, lr, lsl #2] )
  903. movs pc, lr @ branch to handler in SVC mode
  904. ENDPROC(vector_\name)
  905. #ifdef CONFIG_HARDEN_BRANCH_HISTORY
  906. .subsection 1
  907. .align 5
  908. vector_bhb_loop8_\name:
  909. .if \correction
  910. sub lr, lr, #\correction
  911. .endif
  912. @ Save r0, lr_<exception> (parent PC)
  913. stmia sp, {r0, lr}
  914. @ bhb workaround
  915. mov r0, #8
  916. 3: b . + 4
  917. subs r0, r0, #1
  918. bne 3b
  919. dsb
  920. isb
  921. b 2b
  922. ENDPROC(vector_bhb_loop8_\name)
  923. vector_bhb_bpiall_\name:
  924. .if \correction
  925. sub lr, lr, #\correction
  926. .endif
  927. @ Save r0, lr_<exception> (parent PC)
  928. stmia sp, {r0, lr}
  929. @ bhb workaround
  930. mcr p15, 0, r0, c7, c5, 6 @ BPIALL
  931. @ isb not needed due to "movs pc, lr" in the vector stub
  932. @ which gives a "context synchronisation".
  933. b 2b
  934. ENDPROC(vector_bhb_bpiall_\name)
  935. .previous
  936. #endif
  937. .align 2
  938. @ handler addresses follow this label
  939. 1:
  940. .endm
  941. .section .stubs, "ax", %progbits
  942. @ This must be the first word
  943. .word vector_swi
  944. #ifdef CONFIG_HARDEN_BRANCH_HISTORY
  945. .word vector_bhb_loop8_swi
  946. .word vector_bhb_bpiall_swi
  947. #endif
  948. vector_rst:
  949. ARM( swi SYS_ERROR0 )
  950. THUMB( svc #0 )
  951. THUMB( nop )
  952. b vector_und
  953. /*
  954. * Interrupt dispatcher
  955. */
  956. vector_stub irq, IRQ_MODE, 4
  957. .long __irq_usr @ 0 (USR_26 / USR_32)
  958. .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
  959. .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
  960. .long __irq_svc @ 3 (SVC_26 / SVC_32)
  961. .long __irq_invalid @ 4
  962. .long __irq_invalid @ 5
  963. .long __irq_invalid @ 6
  964. .long __irq_invalid @ 7
  965. .long __irq_invalid @ 8
  966. .long __irq_invalid @ 9
  967. .long __irq_invalid @ a
  968. .long __irq_invalid @ b
  969. .long __irq_invalid @ c
  970. .long __irq_invalid @ d
  971. .long __irq_invalid @ e
  972. .long __irq_invalid @ f
  973. /*
  974. * Data abort dispatcher
  975. * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
  976. */
  977. vector_stub dabt, ABT_MODE, 8
  978. .long __dabt_usr @ 0 (USR_26 / USR_32)
  979. .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
  980. .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
  981. .long __dabt_svc @ 3 (SVC_26 / SVC_32)
  982. .long __dabt_invalid @ 4
  983. .long __dabt_invalid @ 5
  984. .long __dabt_invalid @ 6
  985. .long __dabt_invalid @ 7
  986. .long __dabt_invalid @ 8
  987. .long __dabt_invalid @ 9
  988. .long __dabt_invalid @ a
  989. .long __dabt_invalid @ b
  990. .long __dabt_invalid @ c
  991. .long __dabt_invalid @ d
  992. .long __dabt_invalid @ e
  993. .long __dabt_invalid @ f
  994. /*
  995. * Prefetch abort dispatcher
  996. * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
  997. */
  998. vector_stub pabt, ABT_MODE, 4
  999. .long __pabt_usr @ 0 (USR_26 / USR_32)
  1000. .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
  1001. .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
  1002. .long __pabt_svc @ 3 (SVC_26 / SVC_32)
  1003. .long __pabt_invalid @ 4
  1004. .long __pabt_invalid @ 5
  1005. .long __pabt_invalid @ 6
  1006. .long __pabt_invalid @ 7
  1007. .long __pabt_invalid @ 8
  1008. .long __pabt_invalid @ 9
  1009. .long __pabt_invalid @ a
  1010. .long __pabt_invalid @ b
  1011. .long __pabt_invalid @ c
  1012. .long __pabt_invalid @ d
  1013. .long __pabt_invalid @ e
  1014. .long __pabt_invalid @ f
  1015. /*
  1016. * Undef instr entry dispatcher
  1017. * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
  1018. */
  1019. vector_stub und, UND_MODE
  1020. .long __und_usr @ 0 (USR_26 / USR_32)
  1021. .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
  1022. .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
  1023. .long __und_svc @ 3 (SVC_26 / SVC_32)
  1024. .long __und_invalid @ 4
  1025. .long __und_invalid @ 5
  1026. .long __und_invalid @ 6
  1027. .long __und_invalid @ 7
  1028. .long __und_invalid @ 8
  1029. .long __und_invalid @ 9
  1030. .long __und_invalid @ a
  1031. .long __und_invalid @ b
  1032. .long __und_invalid @ c
  1033. .long __und_invalid @ d
  1034. .long __und_invalid @ e
  1035. .long __und_invalid @ f
  1036. .align 5
  1037. /*=============================================================================
  1038. * Address exception handler
  1039. *-----------------------------------------------------------------------------
  1040. * These aren't too critical.
  1041. * (they're not supposed to happen, and won't happen in 32-bit data mode).
  1042. */
  1043. vector_addrexcptn:
  1044. b vector_addrexcptn
  1045. /*=============================================================================
  1046. * FIQ "NMI" handler
  1047. *-----------------------------------------------------------------------------
  1048. * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86
  1049. * systems. This must be the last vector stub, so lets place it in its own
  1050. * subsection.
  1051. */
  1052. .subsection 2
  1053. vector_stub fiq, FIQ_MODE, 4
  1054. .long __fiq_usr @ 0 (USR_26 / USR_32)
  1055. .long __fiq_svc @ 1 (FIQ_26 / FIQ_32)
  1056. .long __fiq_svc @ 2 (IRQ_26 / IRQ_32)
  1057. .long __fiq_svc @ 3 (SVC_26 / SVC_32)
  1058. .long __fiq_svc @ 4
  1059. .long __fiq_svc @ 5
  1060. .long __fiq_svc @ 6
  1061. .long __fiq_abt @ 7
  1062. .long __fiq_svc @ 8
  1063. .long __fiq_svc @ 9
  1064. .long __fiq_svc @ a
  1065. .long __fiq_svc @ b
  1066. .long __fiq_svc @ c
  1067. .long __fiq_svc @ d
  1068. .long __fiq_svc @ e
  1069. .long __fiq_svc @ f
  1070. .globl vector_fiq
  1071. .section .vectors, "ax", %progbits
  1072. .L__vectors_start:
  1073. W(b) vector_rst
  1074. W(b) vector_und
  1075. W(ldr) pc, .L__vectors_start + 0x1000
  1076. W(b) vector_pabt
  1077. W(b) vector_dabt
  1078. W(b) vector_addrexcptn
  1079. W(b) vector_irq
  1080. W(b) vector_fiq
  1081. #ifdef CONFIG_HARDEN_BRANCH_HISTORY
  1082. .section .vectors.bhb.loop8, "ax", %progbits
  1083. .L__vectors_bhb_loop8_start:
  1084. W(b) vector_rst
  1085. W(b) vector_bhb_loop8_und
  1086. W(ldr) pc, .L__vectors_bhb_loop8_start + 0x1004
  1087. W(b) vector_bhb_loop8_pabt
  1088. W(b) vector_bhb_loop8_dabt
  1089. W(b) vector_addrexcptn
  1090. W(b) vector_bhb_loop8_irq
  1091. W(b) vector_bhb_loop8_fiq
  1092. .section .vectors.bhb.bpiall, "ax", %progbits
  1093. .L__vectors_bhb_bpiall_start:
  1094. W(b) vector_rst
  1095. W(b) vector_bhb_bpiall_und
  1096. W(ldr) pc, .L__vectors_bhb_bpiall_start + 0x1008
  1097. W(b) vector_bhb_bpiall_pabt
  1098. W(b) vector_bhb_bpiall_dabt
  1099. W(b) vector_addrexcptn
  1100. W(b) vector_bhb_bpiall_irq
  1101. W(b) vector_bhb_bpiall_fiq
  1102. #endif
  1103. .data
  1104. .align 2
  1105. .globl cr_alignment
  1106. cr_alignment:
  1107. .space 4