dma-isa.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/kernel/dma-isa.c
  4. *
  5. * Copyright (C) 1999-2000 Russell King
  6. *
  7. * ISA DMA primitives
  8. * Taken from various sources, including:
  9. * linux/include/asm/dma.h: Defines for using and allocating dma channels.
  10. * Written by Hennus Bergman, 1992.
  11. * High DMA channel support & info by Hannu Savolainen and John Boyd,
  12. * Nov. 1992.
  13. * arch/arm/kernel/dma-ebsa285.c
  14. * Copyright (C) 1998 Phil Blundell
  15. */
  16. #include <linux/ioport.h>
  17. #include <linux/init.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/io.h>
  20. #include <asm/dma.h>
  21. #include <asm/mach/dma.h>
  22. #define ISA_DMA_MASK 0
  23. #define ISA_DMA_MODE 1
  24. #define ISA_DMA_CLRFF 2
  25. #define ISA_DMA_PGHI 3
  26. #define ISA_DMA_PGLO 4
  27. #define ISA_DMA_ADDR 5
  28. #define ISA_DMA_COUNT 6
  29. static unsigned int isa_dma_port[8][7] = {
  30. /* MASK MODE CLRFF PAGE_HI PAGE_LO ADDR COUNT */
  31. { 0x0a, 0x0b, 0x0c, 0x487, 0x087, 0x00, 0x01 },
  32. { 0x0a, 0x0b, 0x0c, 0x483, 0x083, 0x02, 0x03 },
  33. { 0x0a, 0x0b, 0x0c, 0x481, 0x081, 0x04, 0x05 },
  34. { 0x0a, 0x0b, 0x0c, 0x482, 0x082, 0x06, 0x07 },
  35. { 0xd4, 0xd6, 0xd8, 0x000, 0x000, 0xc0, 0xc2 },
  36. { 0xd4, 0xd6, 0xd8, 0x48b, 0x08b, 0xc4, 0xc6 },
  37. { 0xd4, 0xd6, 0xd8, 0x489, 0x089, 0xc8, 0xca },
  38. { 0xd4, 0xd6, 0xd8, 0x48a, 0x08a, 0xcc, 0xce }
  39. };
  40. static int isa_get_dma_residue(unsigned int chan, dma_t *dma)
  41. {
  42. unsigned int io_port = isa_dma_port[chan][ISA_DMA_COUNT];
  43. int count;
  44. count = 1 + inb(io_port);
  45. count |= inb(io_port) << 8;
  46. return chan < 4 ? count : (count << 1);
  47. }
  48. static struct device isa_dma_dev = {
  49. .init_name = "fallback device",
  50. .coherent_dma_mask = ~(dma_addr_t)0,
  51. .dma_mask = &isa_dma_dev.coherent_dma_mask,
  52. };
  53. static void isa_enable_dma(unsigned int chan, dma_t *dma)
  54. {
  55. if (dma->invalid) {
  56. unsigned long address, length;
  57. unsigned int mode;
  58. enum dma_data_direction direction;
  59. mode = (chan & 3) | dma->dma_mode;
  60. switch (dma->dma_mode & DMA_MODE_MASK) {
  61. case DMA_MODE_READ:
  62. direction = DMA_FROM_DEVICE;
  63. break;
  64. case DMA_MODE_WRITE:
  65. direction = DMA_TO_DEVICE;
  66. break;
  67. case DMA_MODE_CASCADE:
  68. direction = DMA_BIDIRECTIONAL;
  69. break;
  70. default:
  71. direction = DMA_NONE;
  72. break;
  73. }
  74. if (!dma->sg) {
  75. /*
  76. * Cope with ISA-style drivers which expect cache
  77. * coherence.
  78. */
  79. dma->sg = &dma->buf;
  80. dma->sgcount = 1;
  81. dma->buf.length = dma->count;
  82. dma->buf.dma_address = dma_map_single(&isa_dma_dev,
  83. dma->addr, dma->count,
  84. direction);
  85. }
  86. address = dma->buf.dma_address;
  87. length = dma->buf.length - 1;
  88. outb(address >> 16, isa_dma_port[chan][ISA_DMA_PGLO]);
  89. outb(address >> 24, isa_dma_port[chan][ISA_DMA_PGHI]);
  90. if (chan >= 4) {
  91. address >>= 1;
  92. length >>= 1;
  93. }
  94. outb(0, isa_dma_port[chan][ISA_DMA_CLRFF]);
  95. outb(address, isa_dma_port[chan][ISA_DMA_ADDR]);
  96. outb(address >> 8, isa_dma_port[chan][ISA_DMA_ADDR]);
  97. outb(length, isa_dma_port[chan][ISA_DMA_COUNT]);
  98. outb(length >> 8, isa_dma_port[chan][ISA_DMA_COUNT]);
  99. outb(mode, isa_dma_port[chan][ISA_DMA_MODE]);
  100. dma->invalid = 0;
  101. }
  102. outb(chan & 3, isa_dma_port[chan][ISA_DMA_MASK]);
  103. }
  104. static void isa_disable_dma(unsigned int chan, dma_t *dma)
  105. {
  106. outb(chan | 4, isa_dma_port[chan][ISA_DMA_MASK]);
  107. }
  108. static struct dma_ops isa_dma_ops = {
  109. .type = "ISA",
  110. .enable = isa_enable_dma,
  111. .disable = isa_disable_dma,
  112. .residue = isa_get_dma_residue,
  113. };
  114. static struct resource dma_resources[] = { {
  115. .name = "dma1",
  116. .start = 0x0000,
  117. .end = 0x000f
  118. }, {
  119. .name = "dma low page",
  120. .start = 0x0080,
  121. .end = 0x008f
  122. }, {
  123. .name = "dma2",
  124. .start = 0x00c0,
  125. .end = 0x00df
  126. }, {
  127. .name = "dma high page",
  128. .start = 0x0480,
  129. .end = 0x048f
  130. } };
  131. static dma_t isa_dma[8];
  132. /*
  133. * ISA DMA always starts at channel 0
  134. */
  135. void __init isa_init_dma(void)
  136. {
  137. /*
  138. * Try to autodetect presence of an ISA DMA controller.
  139. * We do some minimal initialisation, and check that
  140. * channel 0's DMA address registers are writeable.
  141. */
  142. outb(0xff, 0x0d);
  143. outb(0xff, 0xda);
  144. /*
  145. * Write high and low address, and then read them back
  146. * in the same order.
  147. */
  148. outb(0x55, 0x00);
  149. outb(0xaa, 0x00);
  150. if (inb(0) == 0x55 && inb(0) == 0xaa) {
  151. unsigned int chan, i;
  152. for (chan = 0; chan < 8; chan++) {
  153. isa_dma[chan].d_ops = &isa_dma_ops;
  154. isa_disable_dma(chan, NULL);
  155. }
  156. outb(0x40, 0x0b);
  157. outb(0x41, 0x0b);
  158. outb(0x42, 0x0b);
  159. outb(0x43, 0x0b);
  160. outb(0xc0, 0xd6);
  161. outb(0x41, 0xd6);
  162. outb(0x42, 0xd6);
  163. outb(0x43, 0xd6);
  164. outb(0, 0xd4);
  165. outb(0x10, 0x08);
  166. outb(0x10, 0xd0);
  167. /*
  168. * Is this correct? According to my documentation, it
  169. * doesn't appear to be. It should be:
  170. * outb(0x3f, 0x40b); outb(0x3f, 0x4d6);
  171. */
  172. outb(0x30, 0x40b);
  173. outb(0x31, 0x40b);
  174. outb(0x32, 0x40b);
  175. outb(0x33, 0x40b);
  176. outb(0x31, 0x4d6);
  177. outb(0x32, 0x4d6);
  178. outb(0x33, 0x4d6);
  179. for (i = 0; i < ARRAY_SIZE(dma_resources); i++)
  180. request_resource(&ioport_resource, dma_resources + i);
  181. for (chan = 0; chan < 8; chan++) {
  182. int ret = isa_dma_add(chan, &isa_dma[chan]);
  183. if (ret)
  184. pr_err("ISADMA%u: unable to register: %d\n",
  185. chan, ret);
  186. }
  187. request_dma(DMA_ISA_CASCADE, "cascade");
  188. }
  189. }